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freescale semiconductor data sheet document number: msc8154 rev. 6, 12/2011 ? 2008?2011 freescale semiconductor, inc. msc8154 fc-pbga?783 29 mm 29 mm ? four starcore sc3850 dsp subsystems, each with an sc3850 dsp core, 32 kbyte l1 instruction cache, 32 kbyte l1 data cache, unified 512 kbyte l2 cache configurable as m2 memory in 64 kbyte increments, memory management unit (mmu), extended programmable interrupt controller (epic), two general-purpose 32-bit timers, debug and profiling support, low-power wait, stop, and power-down processing modes, and ecc/edc support. ? chip-level arbitration and switching system (class) that provides full fabric non-blocking arbitration between the cores and other initiators and the m2 memory, shared m3 memory, ddr sram controllers, device configuration control and status registers, maple-b, and other targets. ? 1056 kbyte 128-bit wide m3 memory, 1024 kbytes of which can be turned off to save power. ? 96 kbyte boot rom. ? three input clocks (one global and two differential). ? five plls (three global and two serial rapidio plls). ? multi-accelerator platform engine for baseband (maple-b) with a programmable system interface, turbo decoding, viterbi decoding, and fft/ifft and dft/idft processing. maple-b can be disabled when not required to reduce overall power consumption. ? two ddr controllers with up to a 400 mhz clock (800 mhz data rate), 64/32 bit data bus, supporting up to a total 2 gbyte in up to four banks (two per controller) and support for ddr2 and ddr3. ? dma controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. it is optimized for ddr sdram. ? up to four independent tdm modules with programmable word size (2, 4, 8, or 16-bit), hardware-base a-law/ -law conversion, up to 62.5 mbps data rate for each tdm link, and with glueless interface to e1 or t1 framers that can interface with h-mvip/h.110 devices, tsi, and codecs such as ac-97. ? high-speed serial interface that supports two serial rapidio interfaces, one pci express interface, and two sgmii interfaces (multiplexed). the serial rapidio interfaces support 1x/4x operation up to 3.125 gbaud with a single messaging unit and two dma units. the pci express controller supports 32- and 64-bit addressing, x4, x2, and x1 link. ? quicc engine technology subsystem with dual risc processors, 48 kbyte multi-master ram, 48 kbyte instruction ram, supporting two communication controllers for two gigabit ethernet interfaces (rgmii or sgmii), to offload scheduling tasks from the dsp cores, and an spi. ? i/o interrupt concentrator consolidates all chip maskable interrupt and non-maskable interrupt sources and routes then to int_out , nmi_out , and the cores. ? uart that permits full-duplex operation with a bit rate of up to 6.25 mbps. ? two general-purpose 32-bit timers for rtos support per sc3850 core, four timer modules with four 16-bit fully programmable timers, and eight software watchdog timers (swt). ? eight programmable hardware semaphores. ? up to 32 virtual interrupts and a virtual nmi asserted by simple write access. ?i 2 c interface. ? up to 32 gpio ports, sixteen of which can be configured as external interrupts. ? boot interface options include ethernet, serial rapidio interface, i 2 c, and spi. ? supports standard jtag interface ? low power cmos design, with low-power standby and power-down modes, and optimized power-management circuitry. ? 45 nm soi cmos technology. quad-core digital signal processor
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 2 table of contents 1 pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 fc-pbga ball layout diagram. . . . . . . . . . . . . . . . . . . .4 1.2 signal list by ball location. . . . . . . . . . . . . . . . . . . . . . .5 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.2 recommended operating conditions. . . . . . . . . . . . . .24 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 clkin requirements . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . .26 2.6 ac timing characteristics. . . . . . . . . . . . . . . . . . . . . . .37 3 hardware design considerations . . . . . . . . . . . . . . . . . . . . . .54 3.1 power supply ramp-up sequence . . . . . . . . . . . . . . .54 3.2 pll power supply design considerations . . . . . . . . . .57 3.3 clock and timing signal board layout considerations 58 3.4 sgmii ac-coupled serial link connection example . .58 3.5 connectivity guidelines . . . . . . . . . . . . . . . . . . . . . . . .59 3.6 guide to selecting connections for remote power supply sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 6 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 list of figures figure 1. msc8154 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. starcore sc3850 dsp subsystem block diagram . . . . 3 figure 3. msc8154 fc-pbga package, top view . . . . . . . . . . . . 4 figure 4. differential voltage definitions for transmitter or receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 5. receiver of serdes reference clocks . . . . . . . . . . . . . 30 figure 6. serdes transmitter and re ceiver reference circuits . 31 figure 7. differential reference clock input dc requirements (external dc-coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. differential reference clock input dc requirements (external ac-coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. single-ended reference clock input dc requirements 32 figure 10.sgmii transmitter dc measurement circuit . . . . . . . . . 35 figure 11.ddr2 and ddr3 sdram interface input timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12.mck to mdqs timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 13.ddr sdram output timing . . . . . . . . . . . . . . . . . . . . . 40 figure 14.ddr2 and ddr3 controller bus ac test load. . . . . . . 40 figure 15.ddr2 and ddr3 sdram differential timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16.differential measurement points for rise and fall time 42 figure 17.single-ended measurement points for rise and fall time matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18.single frequency sinusoidal jitter limits . . . . . . . . . . . 44 figure 19.sgmii ac test/measurement load. . . . . . . . . . . . . . . . 45 figure 20.tdm receive signals . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 21.tdm transmit signals . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 22.tdm ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 23.timer ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24.mii management interface timing . . . . . . . . . . . . . . . . . 48 figure 25.rgmii ac timing and multiplexing . . . . . . . . . . . . . . . . 49 figure 26.spi ac test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 27.spi ac timing in slave mode (external clock). . . . . . . 50 figure 28.spi ac timing in master mode (internal clock) . . . . . . 51 figure 29.test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30.boundary scan (jtag) timing . . . . . . . . . . . . . . . . . . . 53 figure 31.test access port timing . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 32.trst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 33.supply ramp-up sequence with v dd ramping before v ddio and clkin starting with v ddio . . . . . . . . . . . . . 54 figure 34.supply ramp-up sequence . . . . . . . . . . . . . . . . . . . . . 56 figure 35.reset connection in functional application . . . . . . . . . 56 figure 36.reset connection in debugger application. . . . . . . . . . 56 figure 37.pll supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 38.serdes pll supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 39.4-wire ac-coupled sgmii serial link connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 40.msc8154 mechanical information, 783-ball fc-pbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 3 figure 1. msc8154 block diagram figure 2. starcore sc3850 dsp subsystem block diagram jtag rmu note: the arrow direction indicates master or slave. ddr interface 64/32-bit 4 tdms dma i/o-interrupt concentrator uart clocks timers reset semaphores other ddr class high-speed serial interface modules quiccengine four tdms 256-channels each 4x 3.125 gbaud boot rom i 2 c virtual interrupts controller spi dma serial dma serial maple-b 4x 3.125 gbaud four dsp cores at 1 ghz turbo/ sgmii viterbi fft/ ifft dft/ idft two sgmii rgmii rgmii m3 memory 1056 kbyte pci-ex 1x/2x/4x subsystem dual risc processors ethernet ethernet spi sc3850 dsp core 512 kbyte 32 kbyte 32 kbyte l1 icache l1 dcache l2 cache / m2 memory rapidio rapidio ddr interface 64/32-bit ddr controller pci expr serdes 1 serdes 2 x2 two sgmii 32 kbyte address translation ta s k protection 32 kbyte (wtb) (wbb) epic interrupts p-bus 128 bit xa-bus 64 bit xb-bus 64-bit dqbus debug support oce30 512 kbyte l2 cache / m2 memory mmu timer 128 bits master iqbus dpu sc3850 core twb write- through buffer write- back buffer instruction cache data cache bus to class 128 bits slave bus from class
msc8154 quad-core digital signal processor data sheet, rev. 6 pin assignment freescale semiconductor 4 1 pin assignment this section includes diagrams of the msc8154 package ball grid array layouts and tables showing how the pinouts are allocated for the package. 1.1 fc-pbga ball layout diagram the top view of the fc-pbga package is shown in figure 3 with the ball location index numbers. figure 3. msc8154 fc-pbga package, top view msc8154 top view 134 2 5678 10 15 13 12 11 9 ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 14 16 17 18 19 20 21 22 23 24 25 26 27 28 ah
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 5 1.2 signal list by ball location table 1 presents the signal list sorted by ball number. when designin g a board, make sure that the power rail for each signal is appropriately considered. the specified power rail must be tied to the voltage level specified in this document if any of the related signal functions are used (active) note: the information in table 1 and table 2 distinguishes among three concepts. first, the power pins are the balls of the device package used to supply specific power levels for di fferent device subsystems (as opposed to signals). second, the power rails are the electrical lines on the board that tran sfer power from the voltage regulators to the device. they are indicated here as the reference power rails for signal lines; therefore, the actual power inputs are listed as n/a with regard to the power rails. third, symbols used in these tables are the names for the voltage levels (absolute, recommended, and so on) and not the power supplies themselves. table 1. signal list by ball number ball number signal name 1,2 pin type 10 power rail name a2 m2dqs3 i/o gvdd2 a3 m2dqs3 i/o gvdd2 a4 m2ecc0 i/o gvdd2 a5 m2dqs 8 i/o gvdd2 a6 m2dqs8 i/o gvdd2 a7 m2a5 ogvdd2 a8 m2ck 1 ogvdd2 a9 m2ck1 ogvdd2 a10 m2cs 0 ogvdd2 a11 m2ba0 ogvdd2 a12 m2cas ogvdd2 a13 m2dq34 i/o gvdd2 a14 m2dqs 4 i/o gvdd2 a15 m2dqs4 i/o gvdd2 a16 m2dq50 i/o gvdd2 a17 m2dqs 6 i/o gvdd2 a18 m2dqs6 i/o gvdd2 a19 m2dq48 i/o gvdd2 a20 m2dq49 i/o gvdd2 a21 vss ground n/a a22 reserved nc ? a23 sxpvdd1 power n/a a24 sxpvss1 ground n/a a25 reserved nc ? a26 reserved nc ? a27 sxcvdd1 power n/a a28 sxcvss1 ground n/a b1 m2dq24 i/o gvdd2 b2 gvdd2 power n/a b3 m2dq25 i/o gvdd2 b4 vss ground n/a b5 gvdd2 power n/a b6 m2ecc1 i/o gvdd2 b7 vss ground n/a b8 gvdd2 power n/a
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 6 b9 m2a13 ogvdd2 b10 vss ground n/a b11 gvdd2 power n/a b12 m2cs 1 ogvdd2 b13 vss ground n/a b14 gvdd2 power n/a b15 m2dq35 i/o gvdd2 b16 vss ground n/a b17 gvdd2 power n/a b18 m2dq51 i/o gvdd2 b19 vss ground n/a b20 gvdd2 power n/a b21 reserved nc ? b22 reserved nc ? b23 sr1_txd0 o sxpvdd1 b24 sr1_txd0 o sxpvdd1 b25 sxcvdd1 power n/a b26 sxcvss1 ground n/a b27 sr1_rxd0 i sxcvdd1 b28 sr1_rxd0 i sxcvdd1 c1 m2dq28 i/o gvdd2 c2 m2dm3 ogvdd2 c3 m2dq26 i/o gvdd2 c4 m2ecc4 i/o gvdd2 c5 m2dm8 ogvdd2 c6 m2ecc2 i/o gvdd2 c7 m2cke1 ogvdd2 c8 m2ck0 ogvdd2 c9 m2ck 0 ogvdd2 c10 m2ba1 ogvdd2 c11 m2a1 ogvdd2 c12 m2we ogvdd2 c13 m2dq37 i/o gvdd2 c14 m2dm4 ogvdd2 c15 m2dq36 i/o gvdd2 c16 m2dq32 i/o gvdd2 c17 m2dq55 i/o gvdd2 c18 m2dm6 ogvdd2 c19 m2dq53 i/o gvdd2 c20 m2dq52 i/o gvdd2 c21 reserved nc ? c22 sr1_imp_cal_rx i sxcvdd1 c23 sxpvss1 ground n/a c24 sxpvdd1 power n/a c25 sr1_ref_clk i sxcvdd1 c26 sr1_ref_clk i sxcvdd1 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 7 c27 reserved nc ? c28 reserved nc ? d1 gvdd2 power n/a d2 vss ground n/a d3 m2dq29 i/o gvdd2 d4 gvdd2 power n/a d5 vss ground n/a d6 m2ecc5 i/o gvdd2 d7 gvdd2 power n/a d8 vss ground n/a d9 m2a8 ogvdd2 d10 gvdd2 power n/a d11 vss ground n/a d12 m2a0 ogvdd2 d13 gvdd2 power n/a d14 vss ground n/a d15 m2dq39 i/o gvdd2 d16 gvdd2 power n/a d17 vss ground n/a d18 m2dq54 i/o gvdd2 d19 gvdd2 power n/a d20 vss ground n/a d21 sxpvss1 ground n/a d22 sxpvdd1 power n/a d23 sr1_txd1 o sxpvdd1 d24 sr1_txd1 o sxpvdd1 d25 sxcvss1 ground n/a d26 sxcvdd1 power n/a d27 sr1_rxd1 i sxcvdd1 d28 sr1_rxd1 i sxcvdd1 e1 m2dq31 i/o gvdd2 e2 m2dq30 i/o gvdd2 e3 m2dq27 i/o gvdd2 e4 m2ecc7 i/o gvdd2 e5 m2ecc6 i/o gvdd2 e6 m2ecc3 i/o gvdd2 e7 m2a9 ogvdd2 e8 m2a6 ogvdd2 e9 m2a3 ogvdd2 e10 m2a10 ogvdd2 e11 m2ras ogvdd2 e12 m2a2 ogvdd2 e13 m2dq38 i/o gvdd2 e14 m2dqs 5 i/o gvdd2 e15 m2dqs5 i/o gvdd2 e16 m2dq33 i/o gvdd2 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 8 e17 m2dq56 i/o gvdd2 e18 m2dq57 i/o gvdd2 e19 m2dqs 7 i/o gvdd2 e20 reserved nc ? e21 reserved nc ? e22 reserved nc ? e23 sxpvdd1 power n/a e24 sxpvss1 ground n/a e25 sr1_pll_agnd 9 ground sxcvss1 e26 sr1_pll_avdd 9 power sxcvdd1 e27 sxcvss1 ground n/a e28 sxcvdd1 power n/a f1 vss ground n/a f2 gvdd2 power n/a f3 m2dq16 i/o gvdd2 f4 vss ground n/a f5 gvdd2 power n/a f6 m2dq17 i/o gvdd2 f7 vss ground n/a f8 gvdd2 power n/a f9 m2ba2 ogvdd2 f10 vss ground n/a f11 gvdd2 power n/a f12 m2a4 ogvdd2 f13 vss ground n/a f14 gvdd2 power n/a f15 m2dq42 i/o gvdd2 f16 vss ground n/a f17 gvdd2 power n/a f18 m2dq58 i/o gvdd2 f19 m2dqs7 i/o gvdd2 f20 gvdd2 power n/a f21 sxpvdd1 power n/a f22 sxpvss1 ground n/a f23 sr1_txd2/sg1_tx 4 o sxpvdd1 f24 sr1_txd2 /s g1_t x 4 o sxpvdd1 f25 sxcvdd1 power n/a f26 sxcvss1 ground n/a f27 sr1_rxd2 /s g1_r x 4 i sxcvdd1 f28 sr1_rxd2/sg1_rx 4 i sxcvdd1 g1 m2dqs 2 i/o gvdd2 g2 m2dqs2 i/o gvdd2 g3 m2dq19 i/o gvdd2 g4 m2dm2 ogvdd2 g5 m2dq21 i/o gvdd2 g6 m2dq22 i/o gvdd2 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 9 g7 m2cke0 ogvdd2 g8 m2a11 ogvdd2 g9 m2a7 ogvdd2 g10 m2ck 2 ogvdd2 g11 m2apar_out ogvdd2 g12 m2odt1 ogvdd2 g13 m2apar_in igvdd2 g14 m2dq43 i/o gvdd2 g15 m2dm5 ogvdd2 g16 m2dq44 i/o gvdd2 g17 m2dq40 i/o gvdd2 g18 m2dq59 i/o gvdd2 g19 m2dm7 ogvdd2 g20 m2dq60 i/o gvdd2 g21 reserved nc ? g22 reserved nc ? g23 sxpvss1 ground n/a g24 sxpvdd1 power n/a g25 sr1_imp_cal_tx i sxcvdd1 g26 sxcvss1 ground n/a g27 reserved nc ? g28 reserved nc ? h1 gvdd2 power n/a h2 vss ground n/a h3 m2dq18 i/o gvdd2 h4 gvdd2 power n/a h5 vss ground n/a h6 m2dq20 i/o gvdd2 h7 gvdd2 power n/a h8 vss ground n/a h9 m2a15 ogvdd2 h10 m2ck2 ogvdd2 h11 m2mdic0 i/o gvdd2 h12 m2vref igvdd2 h13 m2mdic1 i/o gvdd2 h14 m2dq46 i/o gvdd2 h15 m2dq47 i/o gvdd2 h16 m2dq45 i/o gvdd2 h17 m2dq41 i/o gvdd2 h18 m2dq62 i/o gvdd2 h19 m2dq63 i/o gvdd2 h20 m2dq61 i/o gvdd2 h21 reserved nc ? h22 reserved nc ? h23 sr1_txd3/sg2_tx 4 o sxpvdd1 h24 sr1_txd3 /s g2_t x 4 o sxpvdd1 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 10 h25 sxcvss1 ground n/a h26 sxcvdd1 power n/a h27 sr1_rxd3 /s g2_r x 4 i sxcvdd1 h28 sr1_rxd3/sg2_rx 4 i sxcvdd1 j1 m2dqs1 i/o gvdd2 j2 m2dqs 1 i/o gvdd2 j3 m2dq10 i/o gvdd2 j4 m2dq11 i/o gvdd2 j5 m2dq14 i/o gvdd2 j6 m2dq23 i/o gvdd2 j7 m2odt0 ogvdd2 j8 m2a12 ogvdd2 j9 m2a14 ogvdd2 j10 vss ground n/a j11 gvdd2 power n/a j12 vss ground n/a j13 gvdd2 power n/a j14 vss ground n/a j15 gvdd2 power n/a j16 vss ground n/a j17 gvdd2 power n/a j18 vss ground n/a j19 gvdd2 power n/a j20 reserved nc ? j21 reserved nc ? j22 reserved nc ? j23 sxpvdd1 power n/a j24 sxpvss1 ground n/a j25 sxcvdd1 power n/a j26 sxcvss1 ground n/a j27 sxcvdd1 power n/a j28 sxcvss1 ground n/a k1 vss ground n/a k2 gvdd2 power n/a k3 m2dm1 ogvdd2 k4 vss ground n/a k5 gvdd2 power n/a k6 m2dq0 i/o gvdd2 k7 vss ground n/a k8 gvdd2 power n/a k9 m2dq5 i/o gvdd2 k10 vss ground n/a k11 vdd power n/a k12 vss ground n/a k13 vdd power n/a k14 vss ground n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 11 k15 vdd power n/a k16 vss ground n/a k17 vss ground n/a k18 vss ground n/a k19 vdd power n/a k20 reserved nc ? k21 reserved nc ? k22 reserved nc ? k23 sxpvdd2 power n/a k24 sxpvss2 ground n/a k25 sxcvdd2 power n/a k26 sxcvss2 ground n/a k27 sxcvdd2 power n/a k28 sxcvss2 ground n/a l1 m2dq9 i/o gvdd2 l2 m2dq12 i/o gvdd2 l3 m2dq13 i/o gvdd2 l4 m2dqs 0 i/o gvdd2 l5 m2dqs0 i/o gvdd2 l6 m2dm0 ogvdd2 l7 m2dq3 i/o gvdd2 l8 m2dq2 i/o gvdd2 l9 m2dq4 i/o gvdd2 l10 vdd power n/a l11 vss ground n/a l12 m3vdd power n/a l13 vss ground n/a l14 vss ground n/a l15 vss ground n/a l16 vss ground n/a l17 vss ground n/a l18 vdd power n/a l19 vss ground n/a l20 reserved nc ? l21 reserved nc ? l22 reserved nc ? l23 sr2_txd3/pe_txd3/sg2_tx 4 o sxpvdd2 l24 sr2_txd3 /p e_txd3 /s g2_t x 4 o sxpvdd2 l25 sxcvss2 ground n/a l26 sxcvdd2 power n/a l27 sr2_rxd3 /p e_rxd3 /s g2_r x 4 i sxcvdd2 l28 sr2_rxd3/pe_rxd3/sg2_rx 4 i sxcvdd2 m1 m2dq8 i/o gvdd2 m2 vss ground n/a m3 gvdd2 power n/a m4 m2dq15 i/o gvdd2 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 12 m5 m2dq1 i/o gvdd2 m6 vss ground n/.a m7 gvdd2 power n/a m8 m2dq7 i/o gvdd2 m9 m2dq6 i/o gvdd2 m10 vss ground n/a m11 vdd power n/a m12 vss ground n/a m13 vdd power n/a m14 vss ground n/a m15 vss ground n/a m16 vss ground n/a m17 vss ground n/a m18 vss ground n/a m19 vdd power n/a m20 reserved nc ? m21 reserved nc ? m22 reserved nc ? m23 sxpvss2 ground n/a m24 sxpvdd2 power n/a m25 sr2_imp_cal_tx i sxcvdd2 m26 sxcvss2 ground n/a m27 reserved nc ? m28 reserved nc ? n1 vss ground n/a n2 trs t 7 iqvdd n3 porese t 7 iqvdd n4 vss ground n/a n5 tms 7 iqvdd n6 clkout oqvdd n7 vss ground n/a n8 vss ground n/a n9 vss ground n/a n10 vdd power n/a n11 vss ground n/a n12 m3vdd power n/a n13 vss ground n/a n14 vss ground n/a n15 vss ground n/a n16 vdd power n/a n17 vss ground n/a n18 vdd power n/a n19 vss ground n/a n20 reserved nc ? n21 sxpvdd2 power n/a n22 sxpvss2 ground n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 13 n23 sr2_txd2/pe_txd2/sg1_tx 4 o sxpvdd2 n24 sr2_txd2 /p e_txd2 /s g1_t x 4 o sxpvdd2 n25 sxcvdd2 power n/a n26 sxcvss2 ground n/a n27 sr2_rxd2 /p e_rxd2 /s g1_r x 4 i sxcvdd2 n28 sr2_rxd2/pe_rxd2/sg1_rx 4 i sxcvdd2 p1 clkin iqvdd p2 ee0 iqvdd p3 qvdd power n/a p4 vss ground n/a p5 stop_bs iqvdd p6 qvdd power n/a p7 vss ground n/a p8 pll0_avdd 9 power vdd p9 pll2_avdd 9 power vdd p10 vss ground n/a p11 vdd power n/a p12 vss ground n/a p13 vdd power n/a p14 vss ground n/a p15 mvdd power n/a p16 vss ground n/a p17 mvdd power n/a p18 vss ground n/a p19 vdd power n/a p20 reserved nc ? p21 reserved nc ? p22 reserved nc ? p23 sxpvdd2 power n/a p24 sxpvss2 ground n/a p25 sr2_pll_agnd 9 ground sxcvss2 p26 sr2_pll_avdd 9 power sxcvdd2 p27 sxcvss2 ground n/a p28 sxcvdd2 power n/a r1 vss ground n/a r2 nm i iqvdd r3 nmi_ou t 6 oqvdd r4 hrese t 6,7 i/o qvdd r5 int_out 6 oqvdd r6 ee1 oqvdd r7 vss ground n/a r8 pll1_avdd 9 power vdd r9 vss ground n/a r10 vdd power n/a r11 vss non-user n/a r12 vdd power n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 14 r13 vss ground n/a r14 vdd power n/a r15 vss ground n/a r16 mvdd power n/a r17 vss ground n/a r18 vdd power n/a r19 vss ground n/a r20 vss non-user n/a r21 sxpvss2 ground n/a r22 sxpvdd2 power n/a r23 sr2_txd1/pe_txd1 4 o sxpvdd2 r24 sr2_txd1 /p e_txd 1 4 o sxpvdd2 r25 sxcvss2 ground n/a r26 sxcvdd2 power n/a r27 sr2_rxd1 /p e_rxd 1 4 i sxcvdd2 r28 sr2_rxd1/pe_rxd1 4 i sxcvdd2 t1 vss ground n/a t2 tck iqvdd t3 srese t 6,7 i/o qvdd t4 tdi iqvdd t5 vss ground n/a t6 tdo oqvdd t7 vss ground n/a t8 vss ground n/a t9 qvdd power n/a t10 vss ground n/a t11 vdd power n/a t12 vss ground n/a t13 m3vdd power n/a t14 vss ground n/a t15 vdd power n/a t16 vss ground n/a t17 mvdd power n/a t18 vss ground n/a t19 vdd power n/a t20 vss ground n/a t21 vss non-user n/a t22 sr2_imp_cal_rx i sxcvdd2 t23 sxpvss2 ground n/a t24 sxpvdd2 power n/a t25 sr2_ref_clk i sxcvdd2 t26 sr2_ref_clk i sxcvdd2 t27 reserved nc ? t28 reserved nc ? u1 m1dq8 i/o gvdd1 u2 vss ground n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 15 u3 gvdd1 power n/a u4 m1dq15 i/o gvdd1 u5 m1dq1 i/o gvdd1 u6 vss ground n/a u7 gvdd1 power n/a u8 m1dq7 i/o gvdd1 u9 m1dq6 i/o gvdd1 u10 vdd power n/a u11 vss ground n/a u12 m3vdd power n/a u13 vss ground n/a u14 vdd power n/a u15 vss ground n/a u16 vdd power n/a u17 vss ground n/a u18 vdd power n/a u19 vss ground n/a u20 vss ground n/a u21 vss ground n/a u22 vss non-user n/a u23 sr2_txd0/pe_txd0 4 o sxpvdd2 u24 sr2_txd0 /p e_txd0 4 o sxpvdd2 u25 sxcvdd2 power n/a u26 sxcvss2 ground n/a u27 sr2_rxd0 /p e_rxd 0 4 i sxcvdd2 u28 sr2_rxd0/pe_rxd0 4 i sxcvdd2 v1 m1dq9 i/o gvdd1 v2 m1dq12 i/o gvdd1 v3 m1dq13 i/o gvdd1 v4 m1dqs 0 i/o gvdd1 v5 m1dqs0 i/o gvdd1 v6 m1dm0 ogvdd1 v7 m1dq3 i/o gvdd1 v8 m1dq2 i/o gvdd1 v9 m1dq4 i/o gvdd1 v10 vss ground n/a v11 vdd power n/a v12 vss ground n/a v13 vdd power n/a v14 vss ground n/a v15 vdd power n/a v16 vss ground n/a v17 vdd power n/a v18 vss ground n/a v19 vdd power n/a v20 nvdd power n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 16 v21 rcw_lsel_3 /rc20 i/o nvdd v22 r cw_lsel _ 2 /rc19 i/o nvdd v23 sxpvdd2 power n/a v24 sxpvss2 ground n/a v25 r cw_lsel _ 1 /rc18 i/o nvdd v26 rc21 invdd v27 sxcvdd2 power n/a v28 sxcvss2 ground n/a w1 vss ground n/a w2 gvdd1 power n/a w3 m1dm1 ogvdd1 w4 vss ground n/a w5 gvdd1 power n/a w6 m1dq0 i/o gvdd1 w7 vss ground n/a w8 gvdd1 power n/a w9 m1dq5 i/o gvdd1 w10 vdd power n/a w11 vss ground n/a w12 vdd power n/a w13 vss ground n/a w14 vdd power n/a w15 vss ground n/a w16 vdd power n/a w17 vss ground n/a w18 vdd power n/a w19 vss ground n/a w20 vss ground n/a w21 r cw_lsel 0 /rc17 i/o nvdd w22 gpio19/spi_miso 5,8 i/o nvdd w23 vss ground n/a w24 nvdd power n/a w25 gpio11/i rq11 /rc11 5,8 i/o nvdd w26 gpio3/drq1/i rq3 /rc3 5,8 i/o nvdd w27 gpio7/i rq7 /rc7 5,8 i/o nvdd w28 gpio2/i rq2 /rc2 5,8 i/o nvdd y1 m1dqs1 i/o gvdd1 y2 m1dqs 1 i/o gvdd1 y3 m1dq10 i/o gvdd1 y4 m1dq11 i/o gvdd1 y5 m1dq14 i/o gvdd1 y6 m1dq23 i/o gvdd1 y7 m1odt0 ogvdd1 y8 m1a12 ogvdd1 y9 m1a14 ogvdd1 y10 vss ground n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 17 y11 gvdd1 power n/a y12 vss ground n/a y13 gvdd1 power n/a y14 vss ground n/a y15 gvdd1 power n/a y16 vss ground n/a y17 gvdd1 power n/a y18 vss ground n/a y19 gvdd1 power n/a y20 vss ground n/a y21 nvdd power n/a y22 gpio20/s pi_s l 5,8 i/o nvdd y23 gpio17/spi_sck 5,8 i/o nvdd y24 gpio14/drq0/i rq14 /rc14 5,8 i/o nvdd y25 gpio12/i rq12 /rc12 5,8 i/o nvdd y26 gpio8/i rq8 /rc8 5,8 i/o nvdd y27 nvdd power n/a y28 vss ground n/a aa1 gvdd1 power n/a aa2 vss ground n/a aa3 m1dq18 i/o gvdd1 aa4 gvdd1 power n/a aa5 vss ground n/a aa6 m1dq20 i/o gvdd1 aa7 gvdd1 power n/a aa8 vss ground n/a aa9 m1a15 ogvdd1 aa10 m1ck2 ogvdd1 aa11 m1mdic0 i/o gvdd1 aa12 m1vref igvdd1 aa13 m1mdic1 i/o gvdd1 aa14 m1dq46 i/o gvdd1 aa15 m1dq47 i/o gvdd1 aa16 m1dq45 i/o gvdd1 aa17 m1dq41 i/o gvdd1 aa18 m1dq62 i/o gvdd1 aa19 m1dq63 i/o gvdd1 aa20 m1dq61 i/o gvdd1 aa21 vss ground n/a aa22 gpio21 5,8 i/o nvdd aa23 gpio18/spi_mosi 5,8 i/o nvdd aa24 gpio16/rc16 5,8 i/o nvdd aa25 gpio4/ddn1/i rq4 /rc4 5,8 i/o nvdd aa26 gpio9/i rq9 /rc9 5,8 i/o nvdd aa27 gpio6/i rq6 /rc6 5,8 i/o nvdd aa28 gpio1/i rq1 /rc1 5,8 i/o nvdd table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 18 ab1 m1dqs 2 i/o gvdd1 ab2 m1dqs2 i/o gvdd1 ab3 m1dq19 i/o gvdd1 ab4 m1dm2 ogvdd1 ab5 m1dq21 i/o gvdd1 ab6 m1dq22 i/o gvdd1 ab7 m1cke0 ogvdd1 ab8 m1a11 ogvdd1 ab9 m1a7 ogvdd1 ab10 m1ck 2 ogvdd1 ab11 m1apar_out ogvdd1 ab12 m1odt1 ogvdd1 ab13 m1apar_in igvdd1 ab14 m1dq43 i/o gvdd1 ab15 m1dm5 ogvdd1 ab16 m1dq44 i/o gvdd1 ab17 m1dq40 i/o gvdd1 ab18 m1dq59 i/o gvdd1 ab19 m1dm7 ogvdd1 ab20 m1dq60 i/o gvdd1 ab21 vss ground n/a ab22 gpio31/i2c_sda 5,8 i/o nvdd ab23 gpio27/tmr4/rcw_src0 5,8 i/o nvdd ab24 gpio25/tmr2/rcw_src1 5,8 i/o nvdd ab25 gpio24/tmr1/rcw_src2 5,8 i/o nvdd ab26 gpio10/i rq10 /rc10 5,8 i/o nvdd ab27 gpio5/i rq5 /rc5 5,8 i/o nvdd ab28 gpio0/i rq0 /rc0 5,8 i/o nvdd ac1 vss ground n/a ac2 gvdd1 power n/a ac3 m1dq16 i/o gvdd1 ac4 vss ground n/a ac5 gvdd1 power n/a ac6 m1dq17 i/o gvdd1 ac7 vss ground n/a ac8 gvdd1 power n/a ac9 m1ba2 ogvdd1 ac10 vss ground n/a ac11 gvdd1 power n/a ac12 m1a4 ogvdd1 ac13 vss ground n/a ac14 gvdd1 power n/a ac15 m1dq42 i/o gvdd1 ac16 vss ground n/a ac17 gvdd1 power n/a ac18 m1dq58 i/o gvdd1 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 19 ac19 vss ground n/a ac20 gvdd1 power n/a ac21 vss ground n/a ac22 nvdd power n/a ac23 gpio30/i2c_scl 5,8 i/o nvdd ac24 gpio26/tmr3 5,8 i/o nvdd ac25 vss ground n/a ac26 nvdd power n/a ac27 gpio23/tmr0 5,8 i/o nvdd ac28 gpio22 5,8 i/o nvdd ad1 m1dq31 i/o gvdd1 ad2 m1dq30 i/o gvdd1 ad3 m1dq27 i/o gvdd1 ad4 m1ecc7 i/o gvdd1 ad5 m1ecc6 i/o gvdd1 ad6 m1ecc3 i/o gvdd1 ad7 m1a9 ogvdd1 ad8 m1a6 ogvdd1 ad9 m1a3 ogvdd1 ad10 m1a10 ogvdd1 ad11 m1ras ogvdd1 ad12 m1a2 ogvdd1 ad13 m1dq38 i/o gvdd1 ad14 m1dqs 5 i/o gvdd1 ad15 m1dqs5 i/o gvdd1 ad16 m1dq33 i/o gvdd1 ad17 m1dq56 i/o gvdd1 ad18 m1dq57 i/o gvdd1 ad19 m1dqs 7 i/o gvdd1 ad20 m1dqs7 i/o gvdd1 ad21 vss ground n/a ad22 ge2_tx_ctl onvdd ad23 gpio15/ddn0/i rq15 /rc15 5,8 i/o nvdd ad24 gpio13/i rq13 /rc13 5,8 i/o nvdd ad25 ge_mdc onvdd ad26 ge_mdio i/o nvdd ad27 tdm2tck/ge1_td3 3 i/o nvdd ad28 tdm2rck/ge1_td0 3 i/o nvdd ae1 gvdd1 power n/a ae2 vss ground n/a ae3 m1dq29 i/o gvdd1 ae4 gvdd1 power n/a ae5 vss ground n/a ae6 m1ecc5 i/o gvdd1 ae7 gvdd1 power n/a ae8 vss ground n/a table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 20 ae9 m1a8 ogvdd1 ae10 gvdd1 power n/a ae11 vss ground n/a ae12 m1a0 ogvdd1 ae13 gvdd1 power n/a ae14 vss ground n/a ae15 m1dq39 i/o gvdd1 ae16 gvdd1 power n/a ae17 vss ground n/a ae18 m1dq54 i/o gvdd1 ae19 gvdd1 power n/a ae20 vss ground n/a ae21 gpio29/uart_txd 5,8 i/o nvdd ae22 tdm1tck/ge2_rx_clk 3 invdd ae23 tdm1rsn/ge2_rx_ctl 3 i/o nvdd ae24 vss ground n/a ae25 tdm3rck/ge1_gtx_clk 3 i/o nvdd ae26 tdm3tsn/ge1_rx_clk 3 i/o nvdd ae27 tdm2rsn/ge1_td2 3 i/o nvdd ae28 tdm2rdt/ge1_td1 3 i/o nvdd af1 m1dq28 i/o gvdd1 af2 m1dm3 ogvdd1 af3 m1dq26 i/o gvdd1 af4 m1ecc4 i/o gvdd1 af5 m1dm8 ogvdd1 af6 m1ecc2 i/o gvdd1 af7 m1cke1 ogvdd1 af8 m1ck0 ogvdd1 af9 m1ck 0 ogvdd1 af10 m1ba1 ogvdd1 af11 m1a1 ogvdd1 af12 m1we ogvdd1 af13 m1dq37 i/o gvdd1 af14 m1dm4 ogvdd1 af15 m1dq36 i/o gvdd1 af16 m1dq32 i/o gvdd1 af17 m1dq55 i/o gvdd1 af18 m1dm6 ogvdd1 af19 m1dq53 i/o gvdd1 af20 m1dq52 i/o gvdd1 af21 gpio28/uart_rxd 5,8 i/o nvdd af22 tdm0rsn/ge2_td2 3 i/o nvdd af23 tdm0tdt/ge2_td3 3 i/o nvdd af24 nvdd power n/a af25 tdm2tsn/ge1_tx_ctl 3 i/o nvdd af26 ge1_rx_ctl invdd table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 21 af27 tdm2tdt/ge1_tx_clk 3 i/o nvdd af28 tdm3rsn/ge1_rd1 3 i/o nvdd ag1 m1dq24 i/o gvdd1 ag2 gvdd1 power n/a ag3 m1dq25 i/o gvdd1 ag4 vss ground n/a ag5 gvdd1 power n/a ag6 m1ecc1 i/o gvdd1 ag7 vss ground n/a ag8 gvdd1 power n/a ag9 m1a13 ogvdd1 ag10 vss ground n/a ag11 gvdd1 power n/a ag12 m1cs1 ogvdd1 ag13 vss ground n/a ag14 gvdd1 power n/a ag15 m1dq35 i/o gvdd1 ag16 vss ground n/a ag17 gvdd1 power n/a ag18 m1dq51 i/o gvdd1 ag19 vss ground n/a ag20 gvdd1 power n/a ag21 nvdd power n/a ag22 tdm1tsn/ge2_td1 3 i/o nvdd ag23 tdm1rdt/ge2_tx_clk 3 i/o nvdd ag24 tdm0tck/ge2_gtx_clk 3 i/o nvdd ag25 tdm1tdt/ge2_td0 3 i/o nvdd ag26 vss ground n/a ag27 nvdd power n/a ag28 tdm3rdt/ge1_rd0 3 i/o nvdd ah1 reserved. nc ? ah2 m1dqs3 i/o gvdd1 ah3 m1dqs3 i/o gvdd1 ah4 m1ecc0 i/o gvdd1 ah5 m1dqs8 i/o gvdd1 ah6 m1dqs8 i/o gvdd1 ah7 m1a5 ogvdd1 ah8 m1ck1 ogvdd1 ah9 m1ck1 ogvdd1 ah10 m1cs0 ogvdd1 ah11 m1ba0 ogvdd1 ah12 m1ca s ogvdd1 ah13 m1dq34 i/o gvdd1 ah14 m1dqs4 i/o gvdd1 ah15 m1dqs4 i/o gvdd1 ah16 m1dq50 i/o gvdd1 table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 22 ah17 m1dqs6 i/o gvdd1 ah18 m1dqs6 i/o gvdd1 ah19 m1dq48 i/o gvdd1 ah20 m1dq49 i/o gvdd1 ah21 vss ground n/a ah22 tdm0rck/ge2_rd2 3 i/o nvdd ah23 tdm0rdt/ge2_rd3 3 i/o nvdd ah24 tdm0tsn/ge2_rd0 3 i/o nvdd ah25 tdm1rck/ge2_rd1 3 i/o nvdd ah26 tdm3tdt/ge1_rd3 3 i/o nvdd ah27 tdm3tck/ge1_rd2 3 invdd ah28 vss ground n/a notes: 1. reserved signals should be disconnected for compatibility with future revisions of the device. non-user signals are reserved for manufacturing and test purposes only. the assigned signal name is used to indicate whether the signal must be unconnected (reserved), pulled dow n (vss), or pulled up (vdd). 2. signal function during power-on reset is determined by the rcw source type. 3. selection of tdm versus rgmii functionality is determined by the rcw bit values. 4. selection of rapidio, sgmii, and pci express f unctionality is determined by the rcw bit values. 5. selection of the gpio function and other functions is done by gpio register setup. for configuration details, see the gpio chapter in the msc8154 reference manual . 6. open-drain signal. 7. internal 20 k pull-up resistor. 8. for signals with gpio functionality, the open-drain and internal 20 k pull-up resistor can be configured by gpio register programming. see the gpio chapter of the msc8154 reference manual for configuration details. 9. connect to power supply via external filter. see section 3.2 , pll power supply design considerations for details. 10. pin types are: ground = all vss connections; power = all vdd connections; i = input; o = output; i/o = input/output; nc = not connected. table 1. signal list by ball number (continued) ball number signal name 1,2 pin type 10 power rail name
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 23 2 electrical characteristics this document contains detailed information on power co nsiderations, dc/ac electrical characteristics, and ac timing specifications. for addition al information, see the msc8154 reference manual . 2.1 maximum ratings in calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is cal culated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite directio n. therefore, a ?maximum? value for a specification never occurs in the same device with a ?minimum? value for another specification; adding a maximu m to a minimum represents a condition that can never exist. table 2 describes the maximum electri cal ratings for the msc8154. table 2. absolute maximum ratings rating power rail name symbol value unit core supply voltage ? cores 0?3 pll supply voltage 3 vdd v dd v ddpll0 v ddpll1 v ddpll2 ?0.3 to 1.1 ?0.3 to 1.1 ?0.3 to 1.1 ?0.3 to 1.1 v v v v m3 memory supply voltage m3vdd v ddm3 ?0.3 to 1.1 v maple-b supply voltage mvdd v ddm ?0.3 to 1.1 v ddr memory supply voltage ? ddr2 mode ? ddr3 mode ddr reference voltage input ddr voltage gvdd1, gvdd2 mvref v ddddr mv ref v inddr ?0.3 to 1.98 ?0.3 to 1.65 ?0.3 to 0.51 v ddddr ?0.3 to v ddddr + 0.3 v v v v i/o voltage excluding ddr and rapidio lines input i/o voltage nvdd, qvdd v ddio v inio ?0.3 to 2.625 ?0.3 to v ddio + 0.3 v v rapidio pad voltage sxpvdd1, sxpvdd2 v ddsxp ?0.3 to 1.26 v rapid i/o core voltage rapid i/o pll voltage 3 input rapidio i/o voltage sxcvdd1, sxcvdd2 v ddsxc v ddriopll v inrio ?0.3 to 1.21 ?0.3 to 1.21 ?0.3 to v ddsxc + 0.3 v v v operating temperature t j ?40 to 105 c storage temperature range t stg ?55 to +150 c notes: 1. functional operating conditions are given in table 3 . 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the listed limits may affect device reliability or cause permanent damage. 3. pll supply voltage is specified at input of the filter and not at pin of the msc8154 (see figure 37 and figure 38 )
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 24 2.2 recommended operating conditions table 3 lists recommended operating conditions. proper device op eration outside of these conditions is not guaranteed. table 3. recommended operating conditions rating symbol min nominal max unit core supply voltage v dd 0.97 1.0 1.05 v m3 memory supply voltage v ddm3 0.97 1.0 1.05 v maple-b supply voltage v ddm 0.97 1.0 1.05 v ddr memory supply voltage ? ddr2 mode ? ddr3 mode ddr reference voltage v ddddr mv ref 1.7 1.425 0.49 v ddddr 1.8 1.5 0.5 v ddddr 1.9 1.575 0.51 v ddddr v v v i/o voltage excluding ddr and rapidio lines v ddio 2.375 2.5 2.625 v rapid i/o pad voltage v ddsxp 0.97 1.0 1.05 v rapid i/o core voltage v ddsxc 0.97 1.0 1.05 v operating temperature range: ? standard ? higher ? extended t j t j t a t j 0 0 ?40 ? 90 105 ? 105 c c c
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 25 2.3 thermal characteristics table 4 describes thermal characteristics of the msc8154 for the fc-pbga packages. 2.4 clkin requirements table 5 summarizes the required characteristics for the clkin signal. table 4. thermal characteristics for the msc8154 characteristic symbol fc-pbga 29 29 mm 2 unit natural convection 200 ft/min (1 m/s) airflow junction-to-ambient 1, 2 r ja 18 12 c/w junction-to-ambient, four-layer board 1, 2 r ja 13 9 c/w junction-to-board (bottom) 3 r jb 5 c/w junction-to-case 4 r jc 0.6 c/w notes: 1. junction temperature is a func tion of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power di ssipation of other components on the board, and board thermal resistance. 2. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesdc51-6. thermal test board meets jedec specification for the specified package. 3. junction-to-board thermal resistance determined per jedec jesd 51-8. thermal test board m eets jedec specification for the specified package. 4. junction-to-case at the top of the package determined using mi l- std-883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer table 5. clkin requirements parameter/condition 1 symbol min typ max unit notes clkin duty cycle ? 40 ? 60 % 2 clkin slew rate ? 1 ? 4 v/ns 3 clkin peak period jitter ? ? ? 150 ps ? clkin jitter phase noise at ?56 dbc ? ? ? 500 khz 4 ac input swing limits v ac 1.5 ? ? v ? input capacitance c in ??15pf? notes: 1. for clock frequencies, see the clock chapter in the msc8154 reference manual. 2. measured at the rising edge and/or the falling edge at v ddio /2. 3. slew rate as measured from 20% to 80% of voltage swing at clock input. 4. phase noise is calculated as fft of tie jitter.
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 26 2.5 dc electrical characteristics this section describes the dc electrical characteristics for the msc8154. 2.5.1 ddr sdram dc electr ical characteristics this section describes the dc electrical specifications for the ddr sdram interface of the msc8154. note: ddr2 sdram uses v ddddr (typ) = 1.8 v and ddr3 sdram uses v ddddr (typ) = 1.5 v. 2.5.1.1 ddr2 (1.8 v) sdram dc electrical characteristics table 6 provides the recommended operating conditions for th e ddr sdram controller when interfacing to ddr2 sdram. note: at recommended operating conditions (see table 3 ) with v ddddr =1.8v. table 6. ddr2 sdram interface dc electrical characteristics parameter/condition symbol min max unit notes i/o reference voltage mv ref 0.49 v ddddr 0.51 v ddddr v2, 3, 4 input high voltage v ih mv ref + 0.125 v ddddr +0.3 v 5 input low voltage v il ?0.3 m v ref ? 0.125 v 5 i/o leakage current i oz ?50 50 a6 output high current (v out (voh) = 1.37 v) i oh ?13.4 ? ma 7 output low current (v out (vol) = 0.33 v) i ol 13.4 ? ma 7 notes: 1. v ddddr is expected to be within 50 mv of the dram v dd supply voltage at all times. the dram and memory controller can use the same or different sources. 2. mv ref is expected to be equal to 0.5 v ddddr and to track v ddddr dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equa l to mv ref with a minimum value of mv ref ? 0.4 and a maximum value of mv ref + 0.04 v. v tt should track variations in the dc-level of mv ref . 4. the voltage regulator for mv ref must be able to supply up to 300 a. 5. input capacitance load for dq, dqs, and dqs signals are available in the ibis models. 6. output leakage is measured with all outputs are disabled, 0 v v out v ddddr . 7. refer to the ibis model for the complete output iv curve characteristics.
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 27 2.5.1.2 ddr3 (1.5v) sdram dc electrical characteristics table 7 provides the recommended operating conditions for th e ddr sdram controller when interfacing to ddr3 sdram. note: at recommended operating conditions (see table 3 ) with v ddddr =1.5v. 2.5.1.3 ddr2/ddr3 sdram capacitance table 8 provides the ddr controller interface capacitance for ddr2 and ddr3 memory. note: at recommended operating conditions (see table 3 ) with v ddddr = 1.8 v for ddr2 memory or v ddddr =1.5v for ddr3 memory. table 7. ddr3 sdram interface dc electrical characteristics parameter/condition symbol min max unit notes i/o reference voltage mv ref 0.49 v ddddr 0.51 v ddddr v2,3,4 input high voltage v ih mv ref + 0.100 v ddddr v5 input low voltage v il gnd mv ref ? 0.100 v 5 i/o leakage current i oz ?50 50 a6 notes: 1. v ddddr is expected to be within 50 mv of the dram v dd at all times. the dram and memory controller can use the same or different sources. 2. mv ref is expected to be equal to 0.5 v ddddr , and to track v ddddr dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 1% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref with a minimum value of mv ref ? 0.4 and a maximum value of mv ref + 0.04 v. v tt should track variations in the dc-level of mv ref . 4. the voltage regulator for mv ref must be able to supply up to 250 a. 5. input capacitance load for dq, dqs, and dqs signals are available in the ibis models. 6. output leakage is measured with all outputs are disabled, 0 v v out v ddddr . table 8. ddr2/ddr3 sdram capacitance parameter symbol min max unit i/o capacitance: dq, dqs, dqs c io 68pf delta i/o capacitance: dq, dqs, dqs c dio ?0.5pf note: guaranteed by fab proce ss and micro-construction.
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 28 2.5.1.4 ddr reference current draw table 9 lists the current draw characteristics for mv ref . note: values when used at recommended operating conditions (see table 3 ). 2.5.2 high-speed serial interface (hssi) dc electrical characteristics the msc8154 features an hssi that includes two 4-channel serdes ports used for high-speed seri al interface applications (pci express, serial rapidio interfaces, and sgmii). this section a nd its subsections describe the common portion of the serdes dc, including the dc requirements for the serdes reference clocks and the serdes data lane transmitter (tx) and receiver (rx) reference circuits. the data lane circuit specifications are sp ecific for each supported interf ace, and they have individual subsections by protocol. the selection of individual data channel functionality is done via the reset configuration word high register (rcwhr) serdes protocol selection fields (s1p an d s2p). specific ac electrical characteristics are defined in section 2.6.2, ?hssi ac timing specifications .? 2.5.2.1 signal term definitions the serdes interface uses differential signalling to transfer data across the serial link. this section defines terms used in t he description and specification of differential signals. figure 4 shows how the signals are defined. for illustration purposes only, one serdes lane is used in the description. figure 4 shows the waveform for either a transmitter output (sr[1?2]_tx and sr[1?2]_t x ) or a receiver input (sr[1?2]_rx and sr[1?2]_r x ). each signal swings between a volts and b volts where a>b. table 9. current draw characteristics for mv ref parameter / condition symbol min max unit current draw for mv refn ? ddr2 sdram ? ddr3 sdram i mvrefn ? 300 250 a a figure 4. differential voltage definitions for transmitter or receiver differential swing, v id or v od = a ? b a volts b volts differential peak voltage, v diffp = |a ? b| differential peak-peak voltage, v diffpp = 2 v diffp (not shown) sr[1?2]_t x or sr[1?2]_r x sr[1?2]_tx or sr[1?2]_rx v cm = (a + b)/2
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 29 using this waveform, the definitions are listed in table 10 . to simplify the illustration, the definitions assume that the serdes transmitter and receiver operate in a fully symmetrical differential signalling environment. to illustrate these definitions using real values, consider th e example of a current mode logic (cml) transmitter that has a common mode voltage of 2.25 v and outputs, td and td . if these outputs have a swing from 2.0 v to 2.5 v, the peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred to as the single-ended swing for each signal. because the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (v od ) has the same amplitude as each signal single-ended swing. the diffe rential output signal ranges between 500 mv and ?500 mv. in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. table 10. differential signal definitions term definition single-ended swing the transmitter output signals and the receiver input signals sr[1?2]_tx, sr[1?2]_t x , sr[1?2]_rx and sr[1?2]_r x each have a peak-to-peak swing of a ? b volt s. this is also referred to as each signal wire?s single-ended swing. differential output voltage, v od (or differential output swing ): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sr[1?2]_tx ? v sr[1?2]_t x . the v od value can be either positive or negative. differential input voltage, v id (or differential input swing ) the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sr[1?2]_rx ? v sr[1?2]_r x . the v id value can be either positive or negative. differential peak voltage , v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as the differential peak voltage, v diffp = |a ? b| volts. differential peak-to-peak , v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to ?(a ? b) volts, the peak-to -peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p =2 v diffp = 2 |(a ? b)| volts, which is twice the diff erential swing in am plitude, or twice of the differential peak. for example, the output di fferential peak-peak voltage can also be calculated as v tx-diffp-p = 2 |v od |. differential waveform the differential waveform is constructed by subtracting the inverting signal (sr[1?2]_t x , for example) from the non-inverting signal (sr[1?2]_t x , for example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not referenced to ground. refer to figure 16 as an example for differential waveform. common mode voltage, v cm the common mode voltage is equal to half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. in this example, for serdes output, v cm_out =(v sr[1?2]_tx +v sr[1?2]_tx) 2 = (a + b) 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often differ from one component?s output to the other?s input. it may be different between the receiver input and driver output circuits within the same component. it is also referred to as the dc offset on some occasions.
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 30 2.5.2.2 serdes reference clock receiver characteristics the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clock inputs are sr1_ref_clk/sr1_ref_clk or sr2_ref_clk/sr2_ref_clk . figure 5 shows a receiver reference diagram of the serdes reference clocks. the characteristics of the clock signals are as follows: ? the supply voltage requirements for v ddsxc are as specified in table 3 . ? the serdes reference clock receiver reference circuit structure is as follows: ?the sr[1?2]_ref_clk and sr[1?2]_r ef_clk are internally ac-coupled differential inputs as shown in figure 5 . each differential clock input (sr[1?2]_ref_clk or sr[1?2]_r ef_clk ) has on-chip 50- termination to gnd sxc followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be either differen tial or single-ended. refer to the differential mode and single-ended mode descriptions below for detailed requirements. ? the maximum average current requirement also determines the common mode voltage range. ? when the serdes reference clock differential inputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allo wed by the maximum average curr ent of 8 ma because the input is ac-coupled on-chip. ? this current limitation sets the maximum common mode input voltage to be less than 0.4 v (0.4 v / 50 = 8 ma) while the minimum common mode input level is 0.1 v above gnd sxc . for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driv en by its current source from 0 ma to 16 ma (0?0.8 v), such that each phase of the differential input has a si ngle-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sr[1?2]_ref_clk and sr[1?2]_ref_clk inputs cannot drive 50 to gnd sxc dc or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be ac-coupled externally. ? the input amplitude requirement is described in detail in the following sections. figure 5. receiver of serdes reference clocks input amp 50 50 sr[1?2]_ref_clk sr[1?2]_ref_clk
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 31 2.5.2.3 serdes transmitter and receiver reference circuits figure 6 shows the reference circuits for serdes data lane transmitter and receiver. 2.5.3 dc-level requirements for serdes interfaces the following subsections define the dc-level requirements for the serdes reference clocks, the pci express data lines, the serial rapidio data lines, and the sgmii data lines. 2.5.3.1 dc-level requirements for serdes reference clocks the dc-level requirement for the serdes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and serdes refe rence clock inputs, as described below: ? differential mode ? the input amplitude of the differential clock must be between 400 mv and 1600 mv differential peak-peak (or between 200 mv and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing of less than 800 mv and greater than 200 mv. this requirement is the same for both external dc-coupled or ac-coupled connection. ? for an external dc-coupled connection, the maximum average current requirements sets the requirement for average voltage (common mode voltage) as between 100 mv and 400 mv. figure 7 shows the serdes reference clock input requirement for dc-coupled connection scheme. figure 6. serdes transmitter and receiver reference circuits figure 7. differential reference clock input dc requirements (external dc-coupled) 50 50 50 50 transmitter receiver sr[1?2]_txm sr[1?2]_rxm sr[1?2]_t xm sr[1?2]_r xm note: the [1?2] indicates the specific serdes interface (1 or 2) and the m indicates the specific channel within that interface (0,1,2,3). actual signals are assigned by the hrcw assignments at reset (see chapter 5 , reset in the reference manual for details) sr[1?2]_ref_clk sr[1?2]_r ef_clk vmax < 800 mv vmin > 0v 100 mv < vcm < 400 mv 200 mv < input amplitude or differential peak < 800 mv
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 32 ? for an external ac-coupled connection, there is no common mode voltage requirement for the clock driver. because the external ac-coup ling capacitor blocks the dc-level, the cloc k driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connection scheme has its common mode voltage set to gnd sxc . each signal wire of the differential inputs is allowed to swing below and above the command mode voltage gnd sxc . figure 8 shows the serdes reference clock input requirement for ac-coupled connection scheme. ? single-ended mode ? the reference clock can also be single-ended. the sr[1?2]_ref_clk input amplitude (single-ended swing) must be between 400 mv and 800 mv peak-peak (from v min to v max ) with sr[1?2]_r ef_clk either left unconnected or tied to ground. ? the sr[1?2]_ref_clk input average voltage must be between 200 and 400 mv. figure 9 shows the serdes reference clock input requirement for single-ended signalling mode. ? to meet the input amplitude requirement, the reference clock inputs may need to be dc- or ac-coupled externally. for the best noise performance, the reference of the clock could be dc- or ac-coupled into the unused phase (sr[1?2]_r ef_clk ) through the same source impedance as the clock input (sr[1?2]_ref_clk) in use. 2.5.3.2 dc-level requirements for pci express configurations the dc-level requirements for pci express implementations have separate requirements for the tx and rx lines. the msc8154 supports a 2.5 gbps pci express interface defined by the pci express base specification, revision 1.0a . the transmitter specifications are defined in table 11 and the receiver specifications are defined in table 12 . figure 8. differential reference clock input dc requirements (external ac-coupled) figure 9. single-ended reference clock input dc requirements sr[1?2]_ref_clk sr[1?2]_r ef_clk vcm 200 mv < input amplitude or differential peak < 800 mv vmax < vcm + 400 mv vmin > vcm ? 400 mv sr[1?2]_ref_clk sr[1?2]_r ef_clk 400 mv < sr[1?2]_ref_clk input amplitude < 800 mv 0v
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 33 note: specifications are valid at the recomme nded operating conditions listed in table 3 . 2.5.3.3 dc-level requirements for serial rapidio configurations this sections provided various dc-level requirements for serial rapidio configurations. note: specifications are valid at the recomme nded operating conditions listed in table 3 . table 11. pci express (2.5 gbps) differential transmitter (tx) output dc specifications parameter symbol min typical max units notes differential peak-to-peak output voltage v tx-diffp-p 800 1000 1200 mv 1 de-emphasized differential output voltage (ratio) v tx-de-ratio 3.0 3.5 4.0 db 2 dc differential tx impedance z tx-diff-dc 80 100 120 3 transmitter dc impedance z tx-dc 40 50 60 4 notes: 1. v tx-diffp-p = 2 |v tx-d+ ? v tx-d- | measured at the package pins with a test load of 50 to gnd on each pin. 2. ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. measured at the package pins with a test load of 50 to gnd on each pin. 3. tx dc differential mode low impedance 4. required tx d+ as well as d? dc impedance during all states table 12. pci express (2.5 gbps) differential receiver (rx) input dc specifications parameter symbol min typical max units notes differential input peak-to-peak voltage v rx-diffp-p 120 1000 1200 mv 1 dc differential input impedance z rx-diff-dc 80 100 120 2 dc input impedance z rx-dc 40 50 60 3 powered down dc input impedance z rx-high-imp-dc 50 ? ? ? 4 electrical idle detect threshold v rx-idle-det-diffp-p 65 ? 175 mv 5 notes: 1. v rx-diffp-p = 2 |v rx-d+ ? v rx-d- | measured at the package pins with a test load of 50 to gnd on each pin. 2. rx dc differential mode impedance. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of a port. 3. required rx d+ as well as d? dc impedance (50 20% toler ance). measured at the package pins with a test load of 50 to gnd on each pin. impedance during all ltssm states. when transitioning from a fundamental reset to detect (the initial state of the ltssm), there is a 5 ms transition time before the rece iver termination values must be met on all unconfigured lanes of a port. 4. required rx d+ as well as d? dc impedance when the receiv er terminations do not have power. the rx dc common mode impedance that exists when no power is pres ent or fundamental reset is asserted. this helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 5. v rx-idle-det-diffp-p = 2 |v rx-d+ ?v rx-d? |. measured at the package pins of the receiver table 13. serial rapidio transmitter dc specifications parameter symbol min typical max units notes output voltage v o ?0.40 ? 2.30 v 1 long run differential output voltage v diffpp 800 ? 1600 mvp-p ? short run differential output voltage v diffpp 500 ? 1000 mvp-p ? note: voltage relative to common of either signal comprising a differential pair.
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 34 2.5.3.4 dc-level requirements for sgmii configurations note: specifications are valid at the recomme nded operating conditions listed in table 3 table 15 describes the sgmii serdes transmitter ac-coupled dc electrical characteristics. transmitter dc characteristics are measured at the transmitter outputs (sr[1?2]_tx[n] and sr[1?2]_tx [n]) as shown in figure 10 . table 14. serial rapidio receiver dc specifications parameter symbol min typical max units notes differential input voltage v in 200 ? 1600 mvp-p 1 notes: 1. measured at receiver. table 15. sgmii dc transmitter electrical characteristics parameter symbol min typ max unit notes output high voltage v oh ??xv dd_srds-typ /2 + |v od | -max /2 mv 1 output low voltage v ol xv dd_srds-typ /2 ? |v od | -max /2 ? ? mv 1 output differential voltage (xv dd-typ at 1.0 v) |v od | 323 500 725 mv 2,3,4 296 459 665 2,3,5 269 417 604 2,3,6 243 376 545 2,3,7 215 333 483 2,3,8 189 292 424 2,3,9 162 250 362 2,3,10 output impedance (single-ended) r o 40 50 60 ? notes: 1. this does not align to dc-coupled sgmii. xv dd_srds2-typ = 1.1 v. 2. the |v od | value shown in the table assumes full multitude by setting srd_smit_lvl as 000 and the following transmit equalization setting in the xmiteq ab (for lanes a and b) or xmiteq ef (for lanes e and f) bit field of control register: ? the msb (bit 0) of the above bit field is set to zero (selecting the full v dd-diff-p-p amplitude which is power up default); ? the lsb (bit [1?3]) of the above bit field is set based on the equalization settings listed in notes 4 through 10. 3. the |v od | value shown in the typ column is based on the condition of xv dd_srds2-typ = 1.0 v, no common mode offset variation (v os =500mv), serdes transmitter is terminated with 100- differential load between 4. equalization setting: 1.0x: 0000. 5. equalization setting: 1.09x: 1000. 6. equalization setting: 1.2x: 0100. 7. equalization setting: 1.33x: 1100. 8. equalization setting: 1.5x: 0010. 9. equalization setting: 1.71x: 1010. 10. equalization setting: 2.0x: 0110. 11. |v od | = |v sr[1?2]_txn ? v sr[1?2]_t x n |. |v od | is also referred to as output differential peak voltage. v tx-diffp-p = 2*|v od | .
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 35 table 16 describes the sgmii serdes receiver ac-coupled dc electrical characteristics. figure 10. sgmii transmitter dc measurement circuit table 16. sgmii dc receiver electrical characteristics 5 parameter symbol min typ max unit notes dc input voltage range ? n/a ? 1 input differential voltage srdsncr4[eice{12:10}] = 0b001 for sgmii1 srdsncr4[eicf{4:2}] = 0b001 for sgmii2 v rx_diffp-p 100 ? 1200 mv 2, 4 srdsncr4[eice{12:10}] = 0b100 for sgmii1 srdsncr4[eicf{4:2}] = 0b100 for sgmii2 175 ? loss of signal threshold srdsncr4[eice{12:10}] = 0b001 for sgmii1 srdsncr4[eicf{4:2}] = 0b001 for sgmii2 vlos 30 ? 100 mv 3, 4 srdsncr4[eice{12:10}] = 0b100 for sgmii1 srdsncr4[eicf{4:2}] = 0b100 for sgmii2 65 ? 175 receiver differential input impedance z rx_diff 80 ? 120 w ? notes: 1. input must be externally ac-coupled. 2. v rx_diffp-p is also referred to as peak-to- peak input differential voltage. 3. the concept of this parameter is equivalent to the electrical idle detect threshold parameter in the pci express interface. refer to the pci express differential receiver (rx) input specifications section of the pci express specification document. for details. 4. the values for sgmii1 and sgmii2 are selected in the srds control registers. 5. the supply voltage is 1.0 v. 50 transmitter sr[1?2]_txn sr[1?2]_t x n 50 v os v od sgmii serdes interface 50 50
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 36 2.5.4 rgmii and other interface dc electrical characteristics table 17 describes the dc electrical charact eristics for the following interfaces: ?rgmii ethernet ? spi ?tdm ?gpio ? uart ?timer ?ee ?i 2 c ? interrupts (irqn , nmi_out , int_out ) ? clock and resets (clkin, poreset , hreset , sreset ) ? dma external request ?jtag signals table 17. 2.5 v i/o dc electrical characteristics characteristic symbol min max unit notes input high voltage v ih 1.7 ? v 1 input low voltage v il ?0.7 v1 input high current (v in = v ddio )i in ?30 a2 output high voltage (v ddio = min, i oh = ?1.0 ma) v oh 2.0 vddio + 0.3 v 1 output low voltage (v ddio = min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v 1 notes: 1. the min v il and max v ih values are based on the respective min and max v in values listed in table 3 . 2. the symbol v in represents the input voltage of the supply. it is referenced in table 3 .
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 37 2.6 ac timing characteristics this section describes the ac timing characteristics for the msc8154. 2.6.1 ddr sdram ac timing specifications this section describes the ac electrical characteristics for the ddr sdram interface. 2.6.1.1 ddr sdram input ac timing specifications table 18 provides the input ac timing specifications for the ddr sdram when v ddddr (typ) = 1.8 v. table 19 provides the input ac timing specifications for the ddr sdram when v ddddr (typ) = 1.5 v. table 20 provides the input ac timing speci fications for the ddr sdram interface. table 18. ddr2 sdram input ac timing specifications for 1.8 v interface parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.20 v ac input high voltage v ih mv ref + 0.20 ? v note: at recommended operating conditions with v ddddr of 1.8 5%. table 19. ddr3 sdram input ac timing specifications for 1.5 v interface parameter symbol min max unit ac input low voltage v il ?mv ref ? 0.175 v ac input high voltage v ih mv ref + 0.175 ? v note: at recommended operating conditions with v ddddr of 1.5 5%. table 20. ddr sdram input ac timing specifications parameter symbol min max unit notes controller skew for mdqs?mdq/mecc/mdm ? 800 mhz data rate ? 667 mhz data rate t ciskew ?200 ?240 200 240 ps ps 1, 2 tolerated skew for mdqs?mdq/mecc/mdm ? 800 mhz data rate ? 667 mhz data rate t diskew ?425 ?510 425 510 ps ps 2, 3 notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any corresponding bit that is captured with mdqs[n]. subtract this value from the total timing budget. 2. at recommended operating conditions with v ddddr (1.8 v or 1.5 v) 5% 3. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew =(t 4 ? abs(t ciskew )) where t is the clock period and abs(t ciskew ) is the absolute value of t ciskew .
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 38 figure 11 shows the ddr2 and ddr3 sdram interface input timing diagram. 2.6.1.2 ddr sdram output ac timing specifications table 21 provides the output ac timing specifications for the ddr sdram interface. figure 11. ddr2 and ddr3 sdram interface input timing diagram table 21. ddr sdram output ac timing specifications parameter symbol 1 min max unit notes mck[n] cycle time t mck 2.5 5 ns 2 addr/cmd output setup with respect to mck ? 800 mhz data rate ? 667 mhz data rate t ddkhas 0.917 1.10 ? ? ns ns 3 addr/cmd output hold with respect to mck ? 800 mhz data rate ? 667 mhz data rate t ddkhax 0.767 1.02 ? ? ns ns 3 mcsn output setup with respect to mck ? 800 mhz data rate ? 667 mhz data rate t ddkhcs 0.917 1.10 ? ? ns ns 3 mcsn output hold with respect to mck ? 800 mhz data rate ? 667 mhz data rate t ddkhcx 0.767 1.02 ? ? ns ns 3 mck to mdqs skew ? 800 mhz data rate ? 667 mhz data rate t ddkhmh ?0.4 ?0.6 0.375 0.6 ns 4 mdq/mecc/mdm output setup with respect to mdqs ? 800 mhz ? 667 mhz t ddkhds, t ddklds 300 375 ? ? ps ps 5 mdq/mecc/mdm output hold with respect to mdqs ? 800 mhz ? 667 mhz t ddkhdx, t ddkldx 300 375 ? ? ps ps 5 mdqs preamble t ddkhmp ?0.9 t mck ?ns? mdqs postamble t ddkhme ?0.4 t mck ?0.6 t mck ns ? mck [n] mck[n] t mck mdq[n] mdqs[n] t diskew d1 d0 t diskew t diskew
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 39 note: for the addr/cmd setup and hold specifications in table 21 , it is assumed that the clock control register is set to adjust the memory clocks by ? applied cycle. figure 12 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the re ference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made fr om the crossing of the two signals. 3. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. 4. note that t ddkhmh follows the symbol conventions descr ibed in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) clock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. see the msc8154 reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be cent ered inside of the data eye at the pins of the msc8154. 6. at recommended operating conditions with v ddddr (1.5 v or 1,8 v) 5%. figure 12. mck to mdqs timing table 21. ddr sdram output ac ti ming specifications (continued) parameter symbol 1 min max unit notes mdqs mck [n] mck[n] t mck t ddkhmhmax) = 0.6 ns or 0.375 ns t ddkhmh(min) = ?0.6 ns or ?0.375 ns mdqs
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 40 figure 13 shows the ddr sdram output timing diagram. figure 14 provides the ac test load for the ddr2 and ddr3 controller bus. 2.6.1.3 ddr2 and ddr3 sdram differential timing specifications this section describes the dc and ac differential timing specifications for the ddr2 and ddr3 sdram controller interface. figure 15 shows the differential timing specification. note: vtr specifies the true input signal (such as mck or mdqs) and vcp is the complementary input signal (such as mck or mdqs ). figure 13. ddr sdram output timing figure 14. ddr2 and ddr3 controller bus ac test load figure 15. ddr2 and ddr3 sdram differential timing specifications addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp output z 0 = 50 r l = 50 v ddddr /2 vtr vcp gnd gvdd v ox or v ix gv dd /2
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 41 table 22 provides the ddr2 differential specifica tions for the differential signals mdqs/mdqs and mck/mck . table 23 provides the ddr3 differential specifica tions for the differential signals mdqs/mdqs and mck/mck . 2.6.2 hssi ac timing specifications the following subsections define the ac timing requirements fo r the serdes reference clocks, the pci express data lines, the serial rapidio data lines, and the sgmii data lines. 2.6.2.1 ac requirements for serdes reference clock table 24 lists ac requirements for the serdes reference clocks. note: specifications are valid at the recomme nded operating conditions listed in table 3 . table 22. ddr2 sdram differential electrical characteristics parameter symbol min max unit input ac differential cross-point voltage v ixac 0.5 gvdd ? 0.175 0.5 gvdd + 0.175 v output ac differential cross-point voltage v oxac 0.5 gvdd ? 0.125 0.5 gvdd + 0.125 v table 23. ddr3 sdram differential electrical characteristics parameter symbol min max unit input ac differential cross-point voltage v ixac 0.5 gvdd ? 0.150 0.5 gvdd + 0.150 v output ac differential cross-point voltage v oxac 0.5 gvdd ? 0.115 0.5 gvdd + 0.115 v table 24. sr[1?2]_ref_clk and sr[1?2]_r ef_clk input clock requirements parameter symbol min typical max units notes sr[1?2]_ref_clk/sr[1?2]_r ef_clk frequency range t clk_ref ? 100/125 ? mhz 1 sr[1?2]_ref_clk/sr[1?2]_r ef_clk clock frequency tolerance t clk_tol ?350 ? 350 ppm ? sr[1?2]_ref_clk/sr[1?2]_r ef_clk reference clock duty cycle (measured at 1.6 v) t clk_duty 40 50 60 % ? sr[1?2]_ref_clk/sr[1?2]_r ef_clk max deterministic peak-peak jitter at 10 -6 ber t clk_dj ??42ps? sr[1?2]_ref_clk/sr[1?2]_r ef_clk total reference clock jitter at 10 -6 ber (peak-to-peak jitter at ref_clk input) t clk_tj ??86ps2 sr[1?2]_ref_clk/sr[1?2]_r ef_clk rising/falling edge rate t clkrr/ t clkfr 1?4v/ns3 differential input high voltage v ih 200 ? ? mv 4 differential input low voltage v il ? ? ?200 mv 4 rising edge rate (sr[1?2]_ref_clk) to falling edge rate (sr[1?2]_ref_clk) matching rise-fall matching ??20%5, 6
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 42 notes: 1. caution: only 100 and 125 have been tested. other values will not work correctly with the rest of the system. 2. limits from pci express cem rev 1.0a 3. measured from ?200 mv to +200 mv on the differentia l waveform (derived from sr[1?2]_ref_clk minus sr[1?2]_r ef_clk ). the signal must be monotonic through the measurement region for rise and fall time. the 400 mv measurement window is centered on t he differential zero crossing. see figure 16 . 4. measurement taken from differential waveform 5. measurement taken from single-ended waveform 6. matching applies to rising edge for sr[1?2]_ref_clk and falling edge rate for sr[1?2]_r ef_clk . it is measured using a 200 mv window centered on the median cross point where sr[1?2]_ref_clk rising meets sr[1?2]_r ef_clk falling. the median cross point is used to calculate t he voltage thresholds that the oscilloscope uses for the edge rate calculations. the rise edge rate of sr[1?2]_ref_clk should be compared to the fall edge rate of sr[1?2]_ref_clk ; the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 17 . figure 16. differential measurement points for rise and fall time figure 17. single-ended measurement points for rise and fall time matching table 24. sr[1?2]_ref_clk and sr[1?2]_r ef_clk input clock requirements (continued) parameter symbol min typical max units notes v ih = +200 mv v il = ?200 mv 0.0 v sr[1?2]_ref_clk ? sr[1?2]_r ef_clk fall edge rate rise edge rate
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 43 2.6.2.2 pci express ac physical layer specifications the ac requirements for pci express implementations have separate requirements for the tx and rx lines. the msc8154 supports a 2.5 gbps pci express interface defined by the pci express base specification, revision 1.0a . the transmitter specifications are defined in table 25 and the receiver specifications are defined in table 26 . the parameters are specified at the component pins. the ac timing specifications do not include ref_clk jitter. note: specifications are valid at the recomme nded operating conditions listed in table 3 . table 25. pci express (2.5 gbps) differential transmitter (tx) output ac specifications parameter symbol min typical max units notes unit interval ui 399.88 400.00 400.12 ps 1 minimum tx eye width t tx-eye 0.70 ? ? ui 2, 3 maximum time between the jitter median and maximum deviation from the median. t tx-eye-median- to-max-jitter ? ? 0.15 ui 3, 4 ac coupling capacitor c tx 75 ? 200 nf 5 notes: 1. each ui is 400 ps 300 ppm. ui does not account for spread spec trum clock dictated variations. no test load is necessarily associated with this value. 2. the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? t tx-eye = 0.3 ui. 3. specified at the measurement point into a ti ming and voltage compliance test load as shown in figure 8 and measured over any 250 consecutive tx uis. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecut ive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to t he averaged time value. jitter is defi ned as the measurement variation of the crossing points (v tx-diffp-p = 0 v) in relation to a recovered tx ui. a re covered tx ui is calcul ated over 3500 consecutive unit intervals of sample data. 4. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. 5. all transmitters shall be ac-coupled. the ac coupling is required either within the media or within the transmitting component itself. the serdes transmitter does not have built-in tx ca pacitance. an external ac c oupling capacitor is required. table 26. pci express (2.5 gbps) differential receiver (rx) input ac specifications parameter symbol min typical max units notes unit interval ui 399.88 400.00 400.12 ps 1 minimum receiver eye width t rx-eye 0.4 ? ? ui 2, 3, 4 maximum time between the jitter median and maximum deviation from the median. t rx-eye-median-to-max -jitter ? ? 0.3 ui 3, 4, 5 notes: 1. each ui is 400 ps 300 ppm. ui does not account for spread spec trum clock dictated variations. no test load is necessarily associated with this value. 2. the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter =1 ? t rx-eye = 0.6 ui. 3. specified at the measurement point and measured ov er any 250 consecutive uis. the test load in figure 8 should be used as the rx device when taking measurem ents. if the clocks to the rx and tx are not derived from the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 4. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deter ministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same refer ence clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 5. jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0 v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit interv als of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculat ing the tx ui. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consec utive ui interval with a fit algorithm using a minimization merit function. least squares and median deviation fi ts have worked well with experimental and simulated data.
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 44 2.6.2.3 serial rapidio ac timing specifications note: specifications are valid at the recomme nded operating conditions listed in table 3 . table 27 defines the transmitter ac specifications for the serial rapidio interface. the ac timing specifications do not include ref_clk jitter. table 28 defines the receiver ac specifications for the serial ra pidio interface. the ac timing specifications do not include ref_clk jitter. table 27. serial rapidio transmitter ac timing specifications characteristic symbol min typical max unit deterministic jitter j d ? ? 0.17 ui p-p total jitter j t ? ? 0.35 ui p-p unit interval: 1.25 gbaud ui 800 ? 100ppm 800 800 + 100ppm ps unit interval: 2.5 gbaud ui 400 ? 100ppm 400 400 + 100ppm ps unit interval: 3.125 gbaud ui 320 ? 100ppm 320 320 + 100ppm ps table 28. serial rapidio receiver ac timing specifications characteristic symbol min typical max unit notes deterministic jitter tolerance j d 0.37 ? ? ui p-p 1 combined deterministic and random jitter tolerance j dr 0.55 ? ? ui p-p 1 total jitter tolerance j t 0.65 ? ? ui p-p 1, 2 bit error rate ber ? ? 10 ?12 ?? unit interval: 1.25 gbaud ui 800 ? 100ppm 800 800 + 100ppm ps ? unit interval: 2.5 gbaud ui 400 ? 100ppm 400 400 + 100ppm ps ? unit interval: 3.125 gbaud ui 320 ? 100ppm 320 320 + 100ppm ps ? notes: 1. measured at receiver. 2. total jitter is composed of three components, deterministic jitter, random jitter, and single frequency sinusoidal jitter. the sinusoidal jitter may have any amplitude and frequency in the unshaded region of figure 18 . the sinusoidal jitter component is included to ensure margin for low frequency jitter, wander , noise, crosstalk, and other variable system effects. figure 18. single frequency sinusoidal jitter limits 8.5 ui p-p 0.10 ui p-p sinusoidal jitter amplitude 22.1 khz 1.875 mhz 20 mhz frequency
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 45 2.6.2.4 sgmii ac timing specifications note: specifications are valid at the recomme nded operating conditions listed in table 3 . transmitter and receiver ac characteris tics are measured at the transmitter outputs (sr[1?2]_tx[n] and sr[1?2]_tx [n]) or at the receiver inputs (sr[1?2]_rx[n] and sr[1?2]_rx [n]) as depicted in figure 19 , respectively. table 29 provides the sgmii transmit ac timing specifications. a source synchronous clock is not supported. the ac timing specifications do not include ref_clk jitter. table 30 provides the sgmii receiver ac timi ng specifications. the ac timing specifications do not include ref_clk jitter. figure 19. sgmii ac test/measurement load table 29. sgmii transmit ac timing specifications parameter symbol min typ max unit notes deterministic jitter jd ? ? 0.17 ui p-p ? to t a l j i t t e r jt ? ? 0.35 ui p-p 2 unit interval ui 799.92 800 800.08 ps 1 notes: 1. see figure 18 for single frequency sinusoidal jitter limits 2. each ui is 800 ps 100 ppm. table 30. sgmii receive ac timing specifications parameter symbol min typ max unit notes deterministic jitter tolerance jd 0.37 ? ? ui p-p 1, 2 combined deterministic and random jitter tolerance jdr 0.55 ? ? ui p-p 1, 2 total jitter tolerance jt 0.65 ? ? ui p-p 1,2 bit error ratio ber ? ? 10 -12 ?? unit interval ui 799.92 800.00 800.08 ps 3 notes: 1. measured at receiver. 2. refer to rapidio tm 1x/4x lp serial physical layer specification for interpretation of jitter specifications. also see figure 18 . 3. each ui is 800 ps 100 ppm. tx silicon + package d+ package pin d? package pin c = c tx c = c tx r = 50 r = 50
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 46 2.6.3 tdm timing table 31 provides the input and output ac ti ming specifications for the tdm interface. figure 20 shows the tdm receive signal timing. table 31. tdm ac timing specifications for 62.5 mhz 1 parameter symbol 2 min max unit tdmxrck/tdmxtck t dm 16.0 ? ns tdmxrck/tdmxtck high pulse width t dm_high 7.0 ? ns tdmxrck/tdmxtck low pulse width t dm_low 7.0 ? ns tdm all input setup time t dmivkh 3.6 ? ns tdmxrd hold time t dmrdixkh 1.9 ? ns tdmxtfs/tdmxrfs input hold time t dmfsixkh 1.9 ? ns tdmxtck high to tdmxtd output active t dm_outac 2.5 ? ns tdmxtck high to tdmxtd output valid t dmtkhov ?9.8ns tdmxtd hold time t dmtkhox 2.5 ? ns tdmxtck high to tdmxtd output high impedance t dm_outhi ?9.8ns tdmxtfs/tdmxrfs output valid t dmfskhov ?9.25ns tdmxtfs/tdmxrfs output hold time t dmfskhox 2.0 ? ns notes: 1. the symbols used for timing specifications follow the pattern t (first two letters of functional block)(signal)(state)(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t hikhox symbolizes the output internal timing (hi) for the time t serial memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). 2. output values are based on 30 pf capacitive load. 3. inputs are referenced to the sampling that the tdm is progr ammed to use. outputs are referenced to the programming edge they are programmed to use. use of the rising edge or falling edge as a refer ence is programmable. t dmxtck and t dmxrck are shown using the rising edge. 4. all values are based on a maximum tdm interface frequency of 62.5 mhz. figure 20. tdm receive signals tdmxrck tdmxrd tdmxrfs tdmxrfs (output) ~ ~ t dm t dm_high t dm_low t dmivkh t dmivkh t dmrdixkh t dmfsixkh t dmfskhov t dmfskhox
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 47 figure 21 shows the tdm transmit signal timing. figure 22 provides the ac test load for the tdm/si. 2.6.4 timers ac timing specifications table 32 lists the timer input ac timing specifications. note: for recommended operating conditions, see table 3 . figure 23 shows the ac test load for the timers. figure 21. tdm transmit signals figure 22. tdm ac test load table 32. timers input ac timing specifications characteristics symbol minimum unit notes timers inputs?minimum pulse width t tiwid 8ns1, 2 notes: 1. the maximum allowed frequency of timer outputs is 125 mhz. configure the timer modules appropriately. 2. timer inputs and outputs are asynchronous to any visible clock. timer outputs should be synchronized before use by any external synchronous logic. timer inputs are required to be valid for at least t tiwid ns to ensure proper operation. figure 23. timer ac test load tdmxtck tdmxtd ~ ~ ~ ~ tdmxrck tdmxtfs (output) tdmxtfs (input) t dm t dm_high t dm_low t dmivkh t dm_outac t dmfsixkh t dmtkhov t dmtkhox t dm_outhi t dmfskhov t dmfskhox output z 0 = 50 v ddio /2 r l = 50 output z 0 = 50 v ddio /2 r l = 50
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 48 2.6.5 ethernet timing this section describes the ac electrical characteristics for the ethernet interface. there are programmable delay units (pdu) that should be progr ammed differently for each interf ace to meet timing. there is a general configuration register 4 (gcr4) used to conf igure the timing. for additional information, see the msc8154 reference manual . 2.6.5.1 management interface timing table 33 lists the timer input ethernet controller mana gement interface timing specifications shown in figure 24 . table 33. ethernet controller management interface timing characteristics symbol min max unit ge_mdc frequency f mdc ?2.5mhz ge_mdc period t mdc 400 ? ns ge_mdc clock pulse width high t mdc_h 160 ? ns ge_mdc clock pulse width low t mdc_l 160 ? ns ge_mdc to ge_mdio delay 2 t mdkhdx 10 70 ns ge_mdio to ge_mdc rising edge setup time t mddvkh 20 ? ns ge_mdc rising edge to ge_mdio hold time t mddxkh 0?ns notes: 1. program the ge_mdc frequency (f mdc ) to a maximum value of 2.5 mhz (400 ns period for t mdc ). the value depends on the source clock and configuration of miimcfg[mcs] and upsmr[mdcp]. for example, for a source clock of 400 mhz to achieve f mdc = 2.5 mhz, program miimcfg[mcs] = 0x4 and upsmr[mdcp] = 0. see the msc8154 reference manual for configuration details. 2. the value depends on the source clock. for ex ample, for a source clock of 267 mhz, the delay is 70 ns. for a source clock of 333 mhz, the delay is 58 ns. figure 24. mii management interface timing ge_mdc ge_mdio ge_mdio (input) (output) t mdc t mddxkh t mddvkh t mdkhdx t mdc_h t mdc_l
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 49 2.6.5.2 rgmii ac timing specifications table 34 presents the rgmii ac timing specifications for applications requiring an on-board delayed clock. table 35 presents the rgmii ac timing specification for applications required non-delayed clock on board. figure 25 shows the rgmii ac timing and multiplexing diagrams. table 34. rgmii at 1 gbps 2 with on-board delay 3 ac timing specifications parameter/condition symbol min typ max unit data to clock output skew (at transmitter) 4 t skewt ?-0.5 ? 0.5 ns data to clock input skew (at receiver) 4 t skewr 1?2.6ns notes: 1. at recommended operating conditions with v ddio of 2.5 v 5%. 2. rgmii at 100 mbps suppor t is guaranteed by design. 3. program gcr4 as 0x00000000. 4. this implies that pc board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns is added to the associated clock signal. table 35. rgmii at 1 gbps 2 with no on-board delay 3 ac timing specifications parameter/condition symbol min typ max unit data to clock output skew (at transmitter) 4 t skewt ?2.6 ? ?1.0 ns data to clock input skew (at receiver) 4 t skewr ?0.5 ? 0.5 ns notes: 1. at recommended operating conditions with v ddio of 2.5 v 5%. 2. rgmii at 100 mbps suppor t is guaranteed by design. 3. gcr4 should be progr ammed as 0x000cc330. 4. this implies that pc board design requires clocks to be routed with no additional trace delay figure 25. rgmii ac timing and multiplexing gtx_clk t skewt tx_ctl txd[7:4] txd[3:0] (at transmitter) txd[3:0] rx_ctl rxd[8:5] rxd[3:0] rxd[3:0] rx_clk (at receiver) t skewr
msc8154 quad-core digital signal processor data sheet, rev. 6 electrical characteristics freescale semiconductor 50 2.6.6 spi timing table 36 lists the spi input and output ac timing specifications. figure 26 provides the ac test load for the spi. figure 26. spi ac test load figure 27 and figure 28 represent the ac timings from table 36 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 27 shows the spi timings in slave mode (external clock). figure 27. spi ac timing in slave mode (external clock) figure 28 shows the spi timings in master mode (internal clock). table 36. spi ac timing specifications parameter symbol 1 min max unit note spi outputs valid?master mode (internal clock) delay t nikhov ?6ns2 spi outputs hold?master mode (internal clock) delay t nikhox 0.5 ? ns 2 spi outputs valid?slave mode (external clock) delay t nekhov ?12ns2 spi outputs hold?slave mode (external clock) delay t nekhox 2?ns2 spi inputs?master mode (internal clock) input setup time t niivkh 12 ? ns ? spi inputs?master mode (internal clock) input hold time t niixkh 0?ns? spi inputs?slave mode (external clock) input setup time t neivkh 4?ns? spi inputs?slave mode (external clock) input hold time t neixkh 2?ns? notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spiclk clock reference (k) goes to the high state (h) until outputs (o) are invalid (x). 2. output specifications are measured from the 50% level of the rising edge of spiclk to the 50% level of the signal. timings are measured at the pin . output z 0 = 50 v ddio /2 r l = 50 spiclk (input) t neixkh t nekhov input signals: spimosi (see note) output signals: spimiso (see note) t neivkh t nekhox n ote: measured with spmode[ci] = 0, spmode[cp] = 0
electrical characteristics msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 51 figure 28. spi ac timing in master mode (internal clock) spiclk (output) t niixkh t nikhov input signals: spimiso (see note) output signals: spimosi (see note) t niivkh t nikhox n ote: measured with spmode[ci] = 0, spmode[cp] = 0
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 52 2.6.7 asynchronous signal timing table 35 lists the asynchronous signal timing specifications. the following interfaces use the specified asynchronous signals: ? gpio . signals gpio[31?0], when used as gpio signals, that is, when the alternate multiplexed special functions are not selected. note: when used as a general purpose input (gpi), the input signal should be driven until it is acknowledged by the msc8154 device, that is, when th e expected input value is read from the gpio data register. ? ee port. signals ee0, ee1. ? boot function . signal stop_bs. ? i 2 c interface . signals i2c_scl and i2c_sda. ? interrupt inputs . signals irq[15?0] and nmi . ? interrupt outputs . signals int_out and nmi_out (minimum pulse width is 32 ns). 2.6.8 jtag signals table 38 lists the jtag timing specifications shown in figure 29 through figure 32 . figure 29 shows the test clock input timing diagram table 37. signal timing characteristics symbol type min input t in asynchronous one clkin cycle output t out asynchronous application dependent note: input value relevant for ee0, irq[15?0 ], and nmi only. table 38. jtag timing characteristics symbol all frequencies unit min max tck cycle time t tckx 36.0 ? ns tck clock high phase measured at v m = v ddio /2 t tckh 15.0 ? ns boundary scan input data setup time t bsvkh 0.0 ? ns boundary scan input data hold time t bsxkh 15.0 ? ns tck fall to output data valid t tckhov ? 20.0 ns tck fall to output high impedance t tckhoz ? 24.0 ns tms, tdi data setup time t tdivkh 0.0 ? ns tms, tdi data hold time t tdixkh 5.0 ? ns tck fall to tdo data valid t tdohov ? 10.0 ns tck fall to tdo high impedance t tdohoz ? 12.0 ns trst assert time t trst 100.0 ? ns note: all timings apply to once module data transfers as well as any other transfers via the jtag port. figure 29. test clock input timing tck (input) v m v m t tckx t tckh t tckr t tckr
msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 53 figure 30 shows the boundary scan (jtag) timing diagram. figure 31 shows the test access port timing diagram figure 32 shows the trst timing diagram. figure 30. boundary scan (jtag) timing figure 31. test access port timing figure 32. trst timing tck (input) data inputs data outputs data outputs input data valid output data valid t bsxkh t bsvkh t tckhov t tckhoz tck (input) tdi (input) tdo (output) tdo (output) input data valid output data valid tms t tdivkh t tdixkh t tdohov t tdohoz trst (input) t trst
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 54 3 hardware design considerations the following sections discuss areas to consider when the msc8154 device is designed into a system. 3.1 power supply ramp-up sequence the following subsections describe the required device initialization sequence. 3.1.1 clock, reset, and supply coordination starting the device requires coordination between several inputs including: clock, reset, and power supplies. follow this guidelines when starting up an msc8154 device: ? poreset and trst must be asserted externally for the duration of the supply ramp-up, using the v ddio supply. trst deassertion does not have to be synchronized with poreset deassertion. however, trst must be deasserted before normal operation begins to ensure correct functionality of the device. ? clkin should toggle at least 32 cycles before poreset deassertion to guarantee correct device operation. the 32 cycles should only be co unted from the time after v ddio reaches its nominal value (see timing 1 in figure 33 ). ? clkin should either be stable low during ramp-up of v ddio supply (and start its swings after ramp-up) or should swing within v ddio range during v ddio ramp-up, so its amplitude grows as v ddio grows during ramp-up. figure 33 shows a sequence in which v ddio ramps-up after v dd and clkin begins to toggle with the raise of v ddio supply. note: for details on power-on reset flow and duration, see the reset chapter in the msc8154 reference manual . figure 33. supply ramp-up sequence with v dd ramping before v ddio and clkin starting with v ddio voltage time v ddio nominal poreset /trst asserted v dd nominal clkin starts toggling v dd applied poreset deasserted 1 v ddio applied v ddio = nominal v dd = nominal
hardware design considerations msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 55 3.1.2 power-on ramp time this section describes the ac electrical sp ecification for the power-on ramp rate requirements for all voltage supplies (includ ing gvdd/sxpvdd/sxcvdd/qvdd/gvdd/nvdd, all vdd supplies, mvref, and all avdd supplies). controlling the power-on ramp time is required to avoid falsely triggering the esd circuitry. table 39 defines the power supply ramp time specification. 3.1.3 power supply guidelines use the following guidelines for power-up sequencing: ? couple m3vdd with the vdd power rail using an extremely low impedance path. ? couple inputs pll1_avdd, pll2_avdd and pll3_avdd with the vdd power rail using an rc filter (see figure 37 ). ? there is no dependency in power-on/power-off sequence between the gvdd1, gvdd2, nvdd, and qvdd power rails. ? couple inputs m1vref and m2vref with the gvdd1 and gvdd2 power rails, respectively. they should rise at the same time as or after their respective power rail. ? there is no dependency between rapidio supplies: sxcvdd1, sxcvdd2, sxpvdd1 and sxpvdd2 and other msc8154 supplies in the power-on/power-off sequence ? couple inputs sr1_pll_avdd and sr2_pll_avdd with sxcvdd1 and sxcvdd2 power rails, respectively, using an rc filter (see figure 38 ). external voltage applied to any input line must not exceed the i/o supply voltage related to this line by more than 0.6 v at an y time, including during power-up. some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. this is an acceptable exception to the ru le during start-up. however, each such input can draw up to 80 ma per input pin per msc8154 device in the system during power-up. an assertion of the inputs to the high voltage level before power-up should be with slew rate less than 4 v/ns. the device power rails should rise in the following sequence: 1. vdd (and all coupled supplies) table 39. power supply ramp rate parameter min max unit required ramp rate. ? 36000 v/s notes: 1. ramp time is specified as a linear ramp from 10% to 90% of nominal voltage of the specific voltage supply. if the ramp is non-linear (for example, exponential), the maximum rate of c hange from 200 to 500 mv is the most critical because this range might falsely trigger the esd circuitry. 2. required over the full recommended operating temper ature range (see table 3 ). 3. all supplies must be at their stable values within 50 ms. 4. the gvdd pins can be held low on the application board at pow erup. if gvdd is not held low, then gvdd will rise to a voltage level that depends on the board-level impedance-to-ground. if the impedance is high (that is, infinite), then theoretically, gvdd can rise up close to the vdd levels.
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 56 2. after t he above rails rise to 90% of their nominal voltage, the following i/o power rails may rise in any sequence (see figure 34 ): qvdd, nvdd, gvdd1, and gvdd 2. notes: 1. if the m3 memory is not used, m3vdd can be tied to gnd. 2. if the maple-b is not used, mvdd can be tied to gnd. 3. if the hssi port1 is not used, sxcvdd1and sxpvdd1 must be connected to the designated power supplies. 4. if the hssi port2 is not used, sxcvdd2 and sxpvdd2 must be connected to the designated power supplies. 5. if the ddr port 1 interface is not used, it is recommended that gvdd1 be left unconnected. 6. if the ddr port 2 interface is not used, it is recommended that gvdd2 be left unconnected. 3.1.4 reset guidelines when a debugger is not used, implement the connection scheme shown in figure 35 . when a debugger is used, implement the connection scheme shown in figure 36 . figure 34. supply ramp-up sequenc e figure 35. reset connection in functional application figure 36. reset connection in debugger application vdd, mvdd, m3vdd 90% nvdd, qvdd, gvdd1, gvdd2 on-board poreset source trst poreset msc815x (example: voltage monitor) 10 ? on-board poreset source trst poreset msc815x (example: voltage monitor) on-board trst source (example: once) vdd io
hardware design considerations msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 57 3.2 pll power supply design considerations each global pll power supply must have an external rc filter for the plln_avdd input (see figure 37 ) in which the following components are defined as listed: ?r = 5 5% ?c1 = 10 f 10%, 0603, x5r, with esl 0.5 nh, low esl surface mount capacitor. ? c2 = 1.0 f 10%, 0402, x5r, with esl 0.5 nh, low esl surface mount capacitor. note: a higher capacitance value for c2 may be used to improve the filter as long as the other c2 parameters do not change. all three plls can connect to a single supply voltage source (such as a voltage regulator) as long as the external rc filter is applied to each pll separately. for optimal noise filtering, place the circuit as close as possible to its plln_avdd inputs. . each serdes pll power supply must be filtered using a circuit similar to the one shown in figure 38 , to ensure stability of the internal clock. for maximum effectiveness, the filter ci rcuit should be placed as closely as possible to the srn_pll_avdd ball to ensure it filters out as much noise as po ssible. the ground connection should be near the srn_pll_avdd ball. the 0.003 f capacitor is closest to the ball, followed by the two 2.2 f capacitors, and finally the 1 resistor to the board supply plane. the capacitors are connected from srn_pll_avdd to the ground plane. use ceramic chip capacitors with the highest possible self-resonant frequency. all trances should be kept short, wide, and direct. figure 37. pll supplies figure 38. serdes pll supplies msc8156e pll0_avdd r c1 c2 pll1_avdd r c1 c2 pll2_avdd r c1 c2 vdd power rail (voltage regulator) vss vss vss 1 2.2 f 2.2 f 0.003 f srn_pll_avdd srn_pll_agnd as short as possible gnd sxc v ddsxc
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 58 3.3 clock and timing signal board layout considerations when laying out the system board, use the following guidelines: ? keep clock and timing signal paths as short as possible and route with 50 impedance. ? use a serial termination resistor placed close to the cloc k buffer to minimize signal reflection. use the following equation to compute the resistor value: rterm = rim ? rbuf where rim = trace characteristic impedance rbuf = clock buffer internal impedance. 3.4 sgmii ac-coupled serial link connection example figure 39 shows an example of a 4-wire ac-coupled serial link connection. for additional layout suggestions, see an3556 msc815x high speed serial interface hardware design considerations , available on the freescale website or from your local sales office or representative. figure 39. 4-wire ac-coupled sgmii serial link connection example sgmii serdes interface 50 50 transmitter sr[1?2]_tx[[1?2] sr[1?2]_rx[1?2] s r[1?2] _tx[1?2] sr[1?2]_rx[1?2] receiver c tx c tx 50 50 sr[1?2]_rx[1?2] s r[1?2]_ rx[ 1?2]] receiver transmitter sr[1?2]_tx[1?2 ] sr[1?2]_tx[1?2] c tx c tx 50 50 50 50
hardware design considerations msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 59 3.5 connectivity guidelines note: although the package actually uses a ball grid array, the more conventional term pin is used to denote signal connections in this discussion. first, select the pin multiplexing mode to allocate the required i/o signals. then use the guidelines presented in the followin g subsections for board design and connections. the following conventions are used in describing the connectivity requirements: 1. gnd indicates using a 10 k pull-down resistor (recommended) or a dir ect connection to the ground plane. direct connections to the ground plane may yield dc current up to 50 ma through the i/o supply that adds to overall power consumption. 2. v dd indicates using a 10 k pull-up resistor (recommended) or a direct connection to the appropriate power supply. direct connections to the supply may yield dc current up to 50 ma through the i/o supply that adds to overall power consumption. 3. mandatory use of a pull-up or pull-down resistor is clear ly indicated as ?pull-up/pull-down.? for buses, each pin on the bus should have its own resistor. 4. nc indicates ?not connected? and mean s do not connect anything to the pin. 5. the phrase ?in use? indicates a typical pin connection for the required function. note: please see recommendations #1 and #2 as mandatory pull -down or pull-up connection for unused pins in case of subset interface connection.
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 60 3.5.1 ddr memory related pins this section discusses the various scenarios that can be used with either of the msc8154 ddr ports. note: the signal names in table 40 , table 41 and table 42 are generic names for a ddr sdram interface. for actual pin names refer to table 1 . 3.5.1.1 ddr interface is not used table 40. connectivity of ddr related pins when the ddr inte rface is not used signal name pin connection mdq[0?63] nc mdqs[7?0] nc mdq s[ 7?0 ] nc ma[15?0] nc mck[0?2] nc mck [0?2] nc mcs [ 1?0 ] nc mdm[7?0] nc mba[2?0] nc mcas nc mcke[1?0] nc modt[1?0] nc mmdic[1?0] nc mras nc mwe nc mecc[7?0] nc mdm8 nc mdqs8 nc m dqs 8 nc mapar_out nc mapar_in nc mvref 3 nc gvdd1/gvdd2 3 nc notes: 1. for the signals listed in this table, the initial m stand s for m1 or m2 depending on whic h ddr controller is not used. 2. if the ddr controller is not used, disable the internal ddr clock by setting the appropr iate bit in the system clock control register (sccr) and put all ddr i/o in sleep mode by setting drx_gcr[ddrx_doze] (for ddr controller x). see the clocks and general configuration registers chapters in the msc8154 reference manual for details. 3. for msc8154 revision 1 silicon, these pins were connected to gnd. for newer revi sions of the msc8154, connecting these pins to gnd increases device power consumption.
hardware design considerations msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 61 3.5.1.2 ddr interface is used with 32-bit ddr memory only table 41 lists unused pin connection when using 32-bit ddr memory. the 32 most significant data lines are not used. 3.5.1.3 ecc unused pin connections when the error code correction mechan ism is not used in any 32- or 64-bit ddr configuration, refer to table 42 to determine the correct pin connections. table 41. connectivity of ddr related pins when using 32-bit ddr memory only signal name pin connection mdq[31?0] in use mdq[63?32] nc mdqs[3?0] in use mdqs[7?4] nc mdqs[ 3?0] in use mdqs[ 7?4] nc ma[15?0] in use mck[2?0] in use mck[ 2 ? 0 ] in use mcs[ 1?0 ] in use mdm[3?0] in use mdm[7?4] nc mba[2?0] in use mcas in use mcke[1?0] in use modt[1?0] in use mmdic[1?0] in use mras in use mwe in use mvref in use gvdd1/gvdd2 in use notes: 1. for the signals listed in this table, the initial m stand s for m1 or m2 depending on whic h ddr controller is not used. 2. for msc8154 revision 1 silicon, these pins were connected to gnd (or vdd). for newer revisions of the msc8154, connecting these pins to gnd incr eases device power consumption. table 42. connectivity of unused ecc mechanism pins signal name pin connection mecc[7?0] nc mdm8 nc mdqs8 nc m dqs 8 nc notes: 1. for the signals listed in this table, the initial m stand s for m1 or m2 depending on whic h ddr controller is not used. 2. for msc8154 revision 1 silicon, these pins were connected to gnd (or vdd). for newer revisions of the msc8154, connecting these pins to gnd incr eases device power consumption.
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 62 3.5.1.4 ddr2 unused mapar pin connections when the mapar signals are not used, refer to table 43 to determine the correct pin connections. 3.5.2 hssi-related pins 3.5.2.1 hssi port is not used the signal names in table 44 and table 45 are generic names for a rapidio interface. for actual pin names refer to table 1 . 3.5.2.2 hssi specific lane is not used table 43. connectivity of mapar pins for ddr2 signal name pin connection mapar_out nc mapar_in nc notes: 1. for the signals listed in this table, the initial m stands for m1 or m2 depending on which ddr controller is used for ddr2. 2. for msc8154 revision 1 silicon, these pins were connected to gnd. for newer revi sions of the msc8154, connecting these pins to gnd increases device power consumption. table 44. connectivity of serial rapidio interface related pins when the rapidio interface is not used signal name pin connection sr_imp_cal_rx nc sr_imp_cal_tx nc sr[1?2]_r ef_clk sxcvss sr[1?2]_ref_clk sxcvss sr[1?2]_rxd[3?0] sxcvss sr[1?2]_r xd [ 3?0 ] sxcvss sr[1?2]_t x d [ 3?0 ] nc sr[1?2]_txd[3?0] nc sr[1?2]_pll_avdd in use sr[1?2]_pll_agnd in use sxpvss in use sxcvss in use sxpvdd in use sxcvdd in use note: all lanes in the hssi serdes should be powered down. refer to the msc8154 reference manual for details. table 45. connectivity of hssi related pins when specific lane is not used signal name pin connection sr_imp_cal_rx in use sr_imp_cal_tx in use sr[1?2]_r ef_clk in use sr[1?2]_ref_clk in use
hardware design considerations msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 63 3.5.3 rgmii ethernet related pins note: table 46 and table 47 assume that the alternate function of the speci fied pin is not used. if the alternate function is used, connect the pin as required to support that function. ge_mdc and ge_mdio pins should be connected as required by the specified protocol. if neither ge1 nor ge2 is used, table 47 lists the recommended management pin connections. 3.5.4 tdm interface related pins table 48 lists the board connections of the tdm pins when an entire specific tdm is not used. for multiplexing options that select a subset of a tdm interface, use the connections described in table 48 for those signals that are not selected. table 48 assumes that the alternate function of the specified pin is not used. if the alternate function is used, connect that pin as re quired to support the selected function. sr[1?2]_rxd n sxcvss sr[1?2]_rxd n sxcvss sr[1?2]_txd n nc sr[1?2]_txd n nc sr[1?2]_pll_avdd in use sr[1?2]_pll_agnd in use sxpvss in use sxcvss in use sxpvdd in use sxcvdd in use note: the n indicates the lane number {0,1,2,3} for all unused lanes. table 46. connectivity of rgmii related pins when the rgmii interface is not used signal name pin connection ge1_rx_ctl gnd ge2_tx_ctl nc note: assuming ge1 and ge2 are disabled in the reset configuration word. table 47. connectivity of ge management pins when ge1 and ge2 are not used signal name pin connection ge_mdc nc ge_mdio nc table 48. connectivity of tdm related pins when tdm interface is not used signal name pin connection tdm n rclk gnd tdm n rdat gnd tdm n rsyn gnd table 45. connectivity of hssi related pins when specific lane is not used (continued) signal name pin connection
msc8154 quad-core digital signal processor data sheet, rev. 6 hardware design considerations freescale semiconductor 64 3.5.5 miscellaneous pins table 49 lists the board connections for the pins not required by the system design. table 49 assumes that the alternate function of the specified pin is not used. if the alternate function is us ed, connect that pin as required to support the selected funct ion. note: for details on configuration, see the msc8154 reference manual . for additional information, refer to the msc815x and msc825x dsp family design checklist . tdm n tclk gnd tdmt n dat gnd tdm n tsyn gnd v ddio 2.5 v notes: 1. n = {0, 1, 2,3} 2. in case of subset of tdm interface usage pleas e make sure to disable unused tdm modules. see tdm chapter in the msc8154 reference manual for details. table 49. connectivity of individual pins when they are not required signal name pin connection clkout nc ee0 gnd ee1 nc gpio[31?0] nc scl see the gpio connectivity guidelines in this table. sda see the gpio connectivity guidelines in this table. int_out nc irq[15?0] see the gpio connectivity guidelines in this table. nmi v ddio nmi_out nc rc[21?0] gnd stop_bs gnd tck gnd tdi gnd tdo nc tmr[4?0] see the gpio connectivity guidelines in this table. tms gnd trst see section 3.1 for guidelines. urxd see the gpio connectivity guidelines in this table. utxd see the gpio connectivity guidelines in this table. ddn[1?0] see the gpio connectivity guidelines in this table. drq[1?0] see the gpio connectivity guidelines in this table. rcw_lsel_0 gnd rcw_lsel_1 gnd rcw_lsel_2 gnd rcw_lsel_3 gnd v ddio 2.5 v table 48. connectivity of tdm related pins when tdm interface is not used signal name pin connection
ordering information msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 65 3.6 guide to selecting connections for remote power supply sensing to assure consistency of input power levels, some applications use a practice of connecting the remote sense signal input of an on-board power supply to one of power supply pins of the ic device. the advantage of using this connection is the ability to compensate for the slow components of the ir drop caused by resi stive supply current path from on-board power supply to the pins layer on the package. however, because of specific device requirements, not every ball conn ection can be selected as the remote sense pin. some of these pins must be connected to the appropriate power supply or ground to ensure correct device functionality. some connections supply critical power to a speci fic high usage area of the ic die; using such a connection as a non-supply pin could impact necessary supply current during high current events. the following ba lls can be used as the board supply remote sense output without degrading the power and ground supply quality: ? vdd: w10, t19 ? vss: j18, y10 ? m3vdd: none do not use any other connections for remote sensing. use of an y other connections for this purpose can result in application an d device failure. 4 ordering information consult a freescale semiconductor sales office or authorized dist ributor to determine product availability and place an order. part package type spheres core voltage operating temperature core frequency (mhz) order number msc8154 flip chip plastic ball grid array (fc-pbga) lead-free 1.0 v 0 c to 105c 1000 msc8154svt1000b ?40 to 105c 1000 msc8154tvt1000b
msc8154 quad-core digital signal processor data sheet, rev. 6 package information freescale semiconductor 66 5 package information notes: 1. all dimensions in millimeters. 2. dimensioning and tolerancing per asme y14.5m-1994. 3. maximum solder ball diameter measure parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 6. all dimensions are symmetric across the package center lines, unless dimensioned otherwise. 7. 29.2mm maximum package assembly (lid + laminate) x and y. figure 40. msc8154 mechanical information, 783-ball fc-pbga package
product documentation msc8154 quad-core digital signal processor data sheet, rev. 6 freescale semiconductor 67 6 product documentation following is a general list of supporting documentation: ? msc8154 technical data sheet (msc8154). details the signals, ac/dc characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the msc8154 device. ? msc8154 reference manual (msc8154rm). includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. ? application notes . cover various programming topics related to the starcore dsp core and the msc8154 device. ? quicc engine block reference manual with protocol interworking (qeiwrm). provides detailed information regarding the quicc engine technology including functiona l description, registers, and programming information. ? sc3850 dsp core reference manual . covers the sc3850 core architecture, cont rol registers, clock registers, program control, and instruction set. ? msc8156sc3850 dsp core subsystem reference manual . covers core subsystem architecture, functionality, and registers. 7 revision history table 50 provides a revision history for this data sheet. table 50. document revision history rev. date description 0 apr. 2010 ? initial public release. 1 may 2010 ? changed connection for pins k17, l14, l1 6, m15, m17, and n14 from vdd to vss in table 1 . ? updated section 3.1.2 , power-on ramp time . 2 dec 2010 ? updated table 16 . ? updated section 3.1.2 , power-on ramp time . 3mar 2011 ? updated table 8 . ? updated table 15 . ? updated table 17 . ? updated table 33 . ? updated table 35 . ? updated table 39 . 4 may 2011 ? updated table 1 . changed the pin types for the following: ? f25 from ground to power. ? f26 from power to ground. ? t6 from power to o. 5oct 2011 ? updated table 34 and table 35 to reflect 1 gbps and 100 mbps data rate instead of 1 ghz and 100 mhz. 6 dec 2011 ? added note 4 to table 39 .
document number: msc8154 rev. 6 12/2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be va lidated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale, the freescale logo, codewarrior, and starcore are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. quicc engine is a trademark of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2008?2011 freescale semiconductor, inc. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-m eguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 010 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com

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